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1Q falls short at inSilicon; NewLogic gets Bluetooth nod
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Standards-based-core vendor inSilicon Cop. (San Jose) announced that it generated lower-than-expected revenue in December and that earnings and revenue for its first fiscal quarter, ended Dec. 31, will thus fall short of expectations. The company expects earnings before goodwill and other non-cash charges to come in at between 2 cents and 4 cents per share, compared with break-even pro forma results in the year-earlier quarter. Revenue is expected to come in at $6 million, compared with $5.3 million in the same quarter of the prior year.

The company blamed the first quarter's disappointing revenue on the delay of several large customer-license contracts that had been expected by quarter's end. The core vendor is scheduled to release full first-quarter results tomorrow.

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NewLogic Technologies AG (Austria) has successfully completed qualification of its Boost Bluetooth baseband processor core. The qualification tests on the Baseband core and lower level protocol stack were undertaken at 7 Layers AG (Ratingen, Germany), a Bluetooth qualification test facility (BQTF), with final approval granted by Volker Propach, 7 Layers' Bluetooth qualification body.

The Boost core is one of three Bluetooth intellectual property products from NewLogic; the others are a software protocol stack and CMOS radio. According to the company, when the three IP elements are combined with a suitable microcontroller core, they permit the implementation of a single-chip Bluetooth solution using industry-standard CMOS process technologies.

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Programmable-logic-core vendor Adaptive Silicon Inc. (Los Gatos, Calif.) has run its first test chips through LSI Logic Corp.'s 0.18-micron process. Adaptive said its design test chips proved 100 percent functional when manufactured on LSI Logic's G-12 process.

LSI Logic is the initial licensee of, and a primary investor in, Adaptive Silicon's technology. The programmable-logic cores are embeddable silicon intellectual property blocks that can be added to standard-cell designs to provide flexibility and reprogrammability for critical chip functions. Adaptive's software makes it possible to integrate the programmable logic into the overall chip design as well as to map synthesized RTL into the architecture and program the device. See www.adaptivesilicon.com.

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Design And Reuse (D&R; Grenoble, France) is holding a seminar on intellectual property repository building on Jan. 29 at the Marriott Hotel in Santa Clara, Calif.

The seminar will feature a morning session on D&R's IP Catalog Builder and cover IP profiling and repository management with D&R technology. Afternoon sessions will cover data access management and effective use of IP exchanges. The seminar will close with a session titled "The SOC Manager Series: A Mandatory Tool for Planning a Core Centric SOC Project." Register at www.designreuse.com/SEMINAR/registration_ip.html.





The views and opinions expressed in this column are strictly those of the author and should not be taken as an editorial position of EE Times or any of its other editors, publications or Web sites.


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