Axis Systems Inc. (Sunnyvale, Calif.) has rolled out a tool that lets core vendors deliver accelerated, secure and portable cores to customers using the company's verification products.
"We created IP Builder because our customers are doing large system-on-chip designs and need very fast models," said Yukari Chin, director of marketing at Axis. "You can always run models in workstations using slow instruction-set simulators, but that defeats the purpose of using hardware acceleration. Our goal is to help customers keep getting the best performance in verification. At the same time, we can allow core vendors to protect their IP [intellectual property]."
Chin said that IP Builder uses the compiler technology in Axis Systems' products to create a protected binary object model that is mapped into Axis' proprietary ReConfigurable Computing (RCC) elements.
In the Axis scheme, intellectual property suppliers will take the RTL version of their cores and compile it into Axis' RCC database, employing testbenches to verify the core's functionality on Axis emulators or accelerators to validate their cores. Once the cores are fully verified, they then use the IP Builder to essentially encrypt the core model.
"IP Builder uses our proprietary compiler technology and maps only to our reconfigurable RCC elements," Chin said. "This means the model can only be read by Axis customers who own one of our solutions." The core customer then feeds the model to the Axis system, which reads it as an object model.
Chin said that since IP Builder uses the same compiler as Axis Systems' verification products, the precompiled cores are guaranteed to function the same way the IP providers verified them. Chin said that vendors have only to license the IP Builder tool and that the models will be decrypted automatically when entered into the customer's Axis system.
IP Builder will be available in the second quarter with a starting price of $95,000. Visit www.axiscorp.com for further information.
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Processor core vendor Lexra Inc. (San Jose, Calif.) has launched Web-based presentations to detail the three key audio algorithms found in most multimedia integrated circuits: MP3, AC-3 and AAC. The company said the presentations describe the basic audio compression the three algorithms share, their differences and detailed information on their efficient use of the computing resources of the Lexra LX5x80 family of RISC-DSP cores.
According to the company, each of those algorithms contains a mix of integer and DSP math. Both the LX5180 and the LX5280 have sufficient computing resources to handle the audio processing these algorithms require, the company said, with enough headroom to perform other computing tasks as well.
The audio algorithm presentations are available at www.lexra.com/seminars.html.