Timothy O'Donnell, VSIA president and president of ARM Inc., said VSIA plans to use OpenMore in its efforts to create an online metric that will assist users and vendors in developing and integrating quality cores into their designs.

"There is a great concern about the quality of cores that are on the market today," said O'Donnell. "Many people license a core and then later find out that they have to modify the core to fit their specific needs. It is a difficult and expensive thing to accomplish. Everybody wants a metric of the quality of a core-this donation of OpenMore is a big step toward helping us create a more global quality metric."

OpenMore is based on reuse guidelines set out in the "Reuse Methodology Manual," co-authored by Pierre Bricaud, manager of Mentor Graphics European SoC Strategic Relationships, and Synopsys' Michael Keating. O'Donnell said the donation will ensure that the organization's quality group is upgraded in status to an official design working group (DWG).

"We created and developed OpenMore but realize for [it to benefit] the industry, we need to put it in a more formal industry group," Bricaud said. "We think it is in good hands, and to show our commitment, we will take an active role in our efforts in VSIA's Quality DWG."

Synopsys and Mentor Graphics will both have representatives in VSIA's Quality DWG, which plans to use the just-completed work of the VSIA Quality study group and the OpenMore assessment program to create the VSIA Quality Metric that will likely become available by early 2002.

The organization said that there are more than 2,500 users of the OpenMore program and during this transition, VSIA will provide free access to the current OpenMore checklist on the VSIA Web site: www.vsi.org.

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NurLogic Design Inc. has released a compiler-based solution for the rapid generation of I/Os. The company said the new NurLogic's I/O Compiler enables ASIC designers to create a full portfolio of process-specific I/O devices.

The tool provides design and physical elements, creating a comprehensive environment for quality design and exploration. Aimed at ASIC designers, the tool has an easy-to-use interface that lets customers access features for each input, output, bidirectional, three-state, power and ground pad type.

The company claims the I/O physical layout is supported by third-party tools, is silicon proven and can produce 4,000 distinct devices based on the features selected.

NurLogic claims the tool outputs front-end design models, and by automatically implementing the physical back-end views, shortens the product development cycle by allowing quick and easy design exploration.

The tool supports TSMC, UMC and IBM processes for 0.25 micron through 0.13 micron. The I/O Compiler will be available in the third quarter. Pricing starts at $150,000. Visit www.nurlogic.com for more information.