Version 1.1 of the Quartus II design software includes Altera's proprietary LogicLock incremental-design methodology and support for the Apex II family of programmable-logic devices. LogicLock, according to the company, allows designers to preserve fMAX performance at the block level by providing an optimized hierarchical methodology suited for both intellectual-property design and team-based design.

Designers can optimize performance for each design block, lock in the performance and know that timing constraints will always be met after additional design blocks are integrated to complete the system, the company claims.

LogicLock incremental design allows designers to use both fixed and floating regions with multiple levels of hierarchy. User-specified constraints are tied to each region, guaranteeing that the performance of a given region will be preserved when a change is made elsewhere in a design. Those constraints are said to enable better placement and provide the potential to elevate design performance.

The Quartus II software runs on Windows 2000, NT and 98; Sun Solaris; and HP-UX operating systems. A port to Red Hat v.6.2 is pending. Version 1.0 is available as part of the development-tools subscription package. The annual subscription price is $2,000 for a node-locked PC license, which includes Quartus II and MAX+Plus II development software, OEM synthesis tools from Exemplar, OEM simulation tools from Model Technology and 12 months of software upgrades. For subscription information visit www.altera.com.

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Intellectual-property vendor Cast Inc. (Woodcliff Lake, N.J.) says its C16MX750 UART can emulate the function of several popular UART devices while adding IrDA-standard infrared communication functions and extra FIFO memory elements to suit it for a broad range of communications applications. The C16MX750 was developed by Cast partner Moxsyn and is based on the Texas Instruments TL16C750. The core is software-compatible with the 16450 and 16550 UARTs but features extensions. For example, the FIFO mode reduces CPU interrupts by buffering the transmitter and the receiver with programmable 16- or 64-byte FIFOs. And the built-in IrDA-compliant functions enable serial communication with wireless PDAs or network printers through standard infrared ports.

The company said the HDL version of the C16MX750 synthesizes to about 6,500 gates, depending on the target technology. The cores are available in synthesizable VHDL or Verilog or optimized for Altera or Xilinx devices. Pricing varies by deliverable format and technology. The company said licensing is straightforward, flexible and royalty-free. See www.cast-inc.com for more information.