The new core family includes a turbo encoder, a turbo decoder and a full-duplex turbo codec that combines encoding and decoding. All three cores use the Log MAX algorithm.

Adelante offers the cores in synthesizable VHDL or Verilog, verified using Artisan Components' TSMC 0.18-micron standard-cell library. The cores come with cycle-accurate and bit-accurate ANSI C++ or SystemC models for high-speed SoC-level verification. They are also available in high-level C++, in combination with Adelante's A|RT Designer intellectual-property-generation tools, which allow users to generate customized versions for specific applications.

According to the company, the HDL versions of the turbo encoder take 22,890 gates, use 1 kbyte of single-port SRAM and have a maximum system clock of 200 MHz. Meanwhile, the HDL versions of the turbo decoder take 45,300 gates, use 6.3 kbytes of single-port SRAM and have a maximum clock speed of 150 MHz. And the full-duplex turbo codec, with both encoder and decoder, takes 45,600 gates, uses 6.3 kbytes of SRAM and has a maximum clock speed of 150 MHz.

With only 300 more gates than the turbo decoder, the turbo codec is described as a silicon-efficient means for implementing applications that need to perform encoding as well as decoding, either individually or simultaneously. Turbo codec applications include basestation system-on-chip devices, symmetric DSL systems and custom point-to-point connections. The codec also allows Internet-enabled terminals to upload or download images or audio files at the same speed.

The company said it has created a highly parallelized architecture, using its A|RT Designer architectural synthesis methodology, that executes both of the core's MAP decoders in a single clock cycle. The company claims the single-cycle MAP execution gives Adelante's turbo coder core throughput of 1 Mbit per second (based on a 5,114-bit block), with a clock rate of 8.2 MHz and a bit-error rate of 10-6 at a signal-to-noise ratio of 1.5 dB.

The cores are configurable to fully comply with the 3GPP, DVB, DSL or any other turbo-coding standard. The cores start at $70,000. See www.adelantetech.com.

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Pinpoint Solutions Inc. (Boulder, Colo.) is shipping a voice compression core for the emerging "voice over anything" telecom market. The company claims the ADPCM-LCO core will let equipment designers quickly integrate multiple low-bandwidth voice channels using voice compression algorithms based on industry standards.

Integrators of the core will be able to cut time-to-market and cost-per-channel while offloading local digital signal processors for other tasks, according to the company. PSI said it also is working on other cores that will be announced shortly. The eight-person design services house will now apply its experience to intellectual-property products.

For further information see www.asic-design.com.