Axys Design Automation Inc. says its latest modeling platform will let engineers quickly create cycle-accurate, multicore simulation models of system-on-chip (SoC) designs based on the ARM926EJ-S core. With the MaxSim Designer's block diagram editor, users can integrate the ARM926EJ-S core with other models from the Palo Alto, Calif., company's MaxLib component library, such as DSP cores or existing C models imported into the MaxSim environment. Once the platform has been adapted to the specific requirements, SoC architects and software developers can use the MaxSim Control Center to control the simulation of embedded software executing on the new architecture.
Pricing for the full platform, including cycle-callable ARM926EJ-S models, MaxSim Designer, MaxSim Control Center and debuggers, starts at $18,500 a year, under a subscription model. Axys is offering a promotional discount for the package until Oct. 31. See www.axysdesign.com.
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Reconfigurable parallel-coprocessor core vendor Pact Corp. (Santa Clara, Calif.) has implemented a new set of design rules and processes for its Extreme Processor Platform (XPP), increasing the speed and reducing power consumption and area. Using LSI Logic Corp.'s 0.18-micron process library enabled Pact to up clock speed by 33 percent, to 150 MHz or more, while simultaneously reducing the die size requirements for individual parts of the core. The 32-bit ALU, for example, is 1 mm2; the 24-bit ALU is 0.8 mm2.
The XPP targets SoC and DSP designs used in basestations, mobile phones and other devices that require fully reconfigurable, massively parallel-processing capabilities. The company says that power consumption for typical DSP algorithms running on the XPP is between 0.15 and 1.5 watts at the new clock frequency-10 percent of the power draw of many DSP designs. Visit www.pactcorp.com.
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