Mysticom has the technology for both devices, but the cores market for either is still some time off, said David Almagor, Mysticom chief executive. "They are early markets, and right now the integration is at the board level, so people are looking for chips [rather than cores]," he said.

In addition, the physics of high-speed signals makes the market for cores difficult. "At 10 Gbits/s the problem is even more complex because of the high speed," Almagor said. "If you're an IP [intellectual property] vendor and you license the serdes [serializer-deserializer], it's not enough. High-speed packaging is part of the problem, for example."

Finally, power consumption will make integration of gigabit-speed cores difficult for at least the next two generations of devices, Almagor said. Mysticom will continue to sell cores for 10/100-Mbit/s Ethernet, Almagor said.

A marketing agreement between Mentor Graphics Corp. and Austria's NewLogic Technologies AG will let system-on-chip designers license NewLogic's Boost Bluetooth silicon intellectual property from Mentor's Inventra IP division. The cores are available, the companies said, as part of a new Bluetooth platform from Mentor (Wilsonville, Ore.) that features CPU bus wrappers and interface bridges for the Bluetooth core to other IP cores, such as USB 2.0 and Ethernet.

The NewLogic Bluetooth Boost IP family includes a baseband processor and a Bluetooth software protocol stack that can be combined with a suitable microcontroller core to create a single-chip Bluetooth solution.

Complementing the offering, Mentor also has CPU bus wrappers and interface bridges required for the Bluetooth cores that interconnect with other communications IP that is also part of the Inventra IP portfolio. The Bluetooth platform from Mentor is now available. Pricing and a list of Inventra connectivity IP products are available at Mentor's Inventra IP Web site (www.mentor.com/inventra).

Privately held configurable-MPU core vendor Tensilica Inc. has been granted a U.S. patent for a "high-data-density RISC processor." The patent, No. 6,282,633, covers a variety of RISC processor architecture methods, especially those for high-volume, low-cost applications where code density and performance are both critical, the company said.

Covered inventions include the use of large register files with highly packed (< 32-bit) instructions, dense encoding of multiple operations per instruction and use of mode-less variable-length RISC instructions to reduce code size and power without compromising performance. All these techniques, the company said, are now employed in Tensilica's Xtensa configurable-processor family and may also prove valuable for a broad range of other high-density processor architectures the company may develop.

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Edited by Michael Santarini, with a lead contribution from Craig Matsumoto.