Sonics Inc. is touting what it calls a new category of intellectual-property (IP) core that allows system-on-chip designers to better control memory performance in Sonics' MicroNetwork SiliconBackplane. The MemMax Memory Scheduler gives designers control over memory subsystems that are now awkwardly shared by the multiple, contentious processors typically used in SoC designs, said Ed Smith, vice president of marketing at Sonics.

The scheduler core is positioned between any memory controller interfaced with the Open Core Protocol and the Sonics SiliconBackplane MicroNetwork. In the MicroNetwork, users packetize a given core and link it to other cores via the backplane. Bundled in each packetized core, Smith said, is information such as thread identifiers and data on how much access the core needs to the off-chip RAM to work effectively.

"What we haven't had until now is a scheduler that is able to interpret that information, realize memory efficiency requirements and assign given cores the appropriate amount of RAM access they need to work optimally," he said.

Smith said that in Sonics' SoC Creator environment, users access a graphical user interface and specify criteria for quality of service (QoS) "on a per-thread basis." They also specify "how they want the DRAM subsystem to operate," he said.

At the heart of the core is a three-tiered filtering system that, with user guidance, arranges signals by importance, said Hayssam Balach, director of product marketing. In the first tier, called Priority, users identify which signals are most important-those that need to be serviced by RAM most often or those that are performance critical. The second tier, called Allocated Bandwidth, identifies and then assigns bandwidth for each signal to work properly. If signals are equal in bandwidth and priority, the filter moves them to a tier called Best Effort that allows users to essentially decide which should receive QoS from the RAM in a pinch. "You can say one net requires 20 percent of the bandwidth or DRAM access, but beyond that its priority is no longer this high and it can fall into Best Effort," Balach said.

Sonics' MemMax memory scheduler core is available immediately at a per-design license fee starting at $75,000 list. Visit (www.sonics.com.)

Library vendor Virtual Silicon Technology has received $20 million in venture funding. The company also announced that it has qualified its 0.13- and 0.18-micron standard-cell libraries for Synopsys Inc.'s PrimeTime SI static timing-analysis tool. Virtual Silicon and Synopsys said that the libraries, characterized with Silicon Metrics Corp.'s SiliconSmart CR tool, offer users a fast adoption path to PrimeTime SI for full-chip crosstalk analysis.

To support this advanced analysis, Synopsys and Silicon Metrics collaborated on crosstalk characterization and modeling techniques, enabling Virtual Silicon to use SiliconSmart CR to generate Liberty (.lib-format) eSi-Route libraries qualified for PrimeTime SI. The companies have verified that when tested with PrimeTime SI, the libraries met the characterization guidelines and provided Spice-level accuracy.