Xilinx Inc. has enhanced its 1- and 10-Gbit Ethernet media-access controller cores to work in its Virtex-II Pro platform field-programmable gate arrays. Xilinx has upgraded both MAC cores to provide designers with a gigabit serial-interface option, along with an enhanced network-management feature set that supports programmable interframe gaps, EtherStats-based statistics and jumbo frames.
Xilinx designed the 10-Gbit Ethernet core to Draft 4.1 of the IEEE P802.3ae specification. This core, called 10 GMAC, includes the option of either a parallel 10-Gbit media independent interface (XGMII) or a serial 10-Gbit attachment unit interface (Xaui). The company said that with the inclusion of the Xaui interface, the 10 GMAC can support 10G Base X applications without need for an external serial physical-layer device. This combination, said Xilinx, reduces overall system costs and design complexity. The company said the 10 GMAC is fit for emerging 10-Gbit equipment as an alternative to Sonet for wide-area network systems.
With its integrated physical-coding sublayer and physical media attachment functions running at 1.25 Gbits/second, the 1-Gbit core can be configured to create a single-chip 1,000 Base X solution, suited for the development of gigabit communication and storage equipment. The 1 GMAC core also incorporates an 8-bit parallel GMII interface running at 125 MHz to provide up to 1-Gbit/s total bandwidth.
The two cores are available now as LogiCore products under terms of the company's sign-once intellectual-property license. They can be downloaded from www.xilinx.com/ipcenter. The license price is $22,000 for the 10 GMAC and $16,000 for the 1 GMAC. Both are available for use in the Virtex-II series of platform FPGAs as well as Virtex-E and Spartan-IIE families of FPGAs. Xilinx is a principal member of the IEEE P802.3ae 10Gb Ethernet Task Force, working with networking system and IC developers on current and future versions of the standard to ensure interoperability.
Mitsubishi Electric Corp. has licensed from ARM Ltd. the ARM926EJ-S processor core, which incorporates the Jazelle technology for Java acceleration, in a bid to provide semiconductor customers with a low-power solution for wireless applications such as mobile phones and PDAs.
Mitsubishi plans to combine the ARM microprocessor core with its own high-capacity embedded-memory technology to give developers an ASIC system solution.
The ARM Jazelle technology is claimed to accelerate Java execution by up to eight times compared with a fully software-based Java virtual machine. The ARM926EJ-S core runs on diverse platform operating systems such as Linux, Palm OS, Windows CE and Symbian OS in mobile phones or other applications. It is fully synthesizable, enabling its use with several generations of process technology. It also features selectable-size instruction and data caches as well as tightly coupled memory interfaces. To further ease development of a complex system-on-chip, an embedded trace macrocell interface and an Amba Advanced High-performance Bus on-chip interconnect interface are provided.
Visit www.mitsubishielectric.com and www.arm.com for more information.