TriCN's DDR FCRAM uses the company's interface-specific approach to I/O. Whereas many suppliers provide I/O products in a generic form, such as SSTL-2, TriCN delivers I/Os already optimized for a specific interface, in this case DDR FCRAM. This, according to TriCN, saves customers development time and money, and ensures that the interface will meet all performance requirements.

Interface-specific I/O is TriCN's way of distinguishing its suite of high-performance interfaces from what's available from generic I/O IP providers.

The DDR FCRAM is based on a standard advanced by the Joint Electronic Device Engineering Council, and consists of SSTL-2 I/O pads including dedicated I/O drivers for data, clock and address.

According to TriCN, the interface's maximum operational frequency varies from 600 to 666 Mbits/second per I/O depending on the geometry and process targeted by the user. The company provides users with an internal Vref generator for wafer and module test applications.

TriCN also performs rigorous system-level signal integrity and timing analysis to make sure the interface provides reliable, optimal performance.

According to the company, each interface is qualified for timing completeness and signal integrity quality for a full range of printed-circuit board impedance, pc board route lengths, terminator tolerance and topology for given operational frequencies and memory sizes.

As an option, delivery may include system layout application notes. The company also provides an HSpice analysis environment to customers wishing to perform further analyses as modifications are made to the system.

TriCN's DDR FCRAM is available in Taiwan Semiconductor Manufacturing Co.'s 0.18-micron and 0.15-micron processes and several variations of its 0.13-micron processes, including the 1-volt core supply (low-voltage) process. Visit www.tricn.com for more information.

Xilinx Inc. and Paxonet Communications Inc. announced the availability of an STS-192 Sonet IP core package for programmable logic.

The Paxonet solution entails complete STS-192 Sonet framing and path processing. The new cores are optimized for Xilinx Virtex-II and Virtex-II Pro field-programmable gate arrays and have been validated for supporting full STS-192 Sonet/SDH speeds on programmable logic devices.

Target applications at the metropolitan edges of the network include multiservice switches, regenerators, path terminators, add-drop multiplexers, digital cross-connects, traffic aggregators and Sonet test equipment.

According to the companies, the STS-192 IP cores comply with ITU G.707, G.783, BellCore GR253 and ANSI T1.105 standards and offer Sonet framing and path-processing support. The cores are available directly from Paxonet Communications. Visit www.xilinx.com/ipcenter for more information.