ARM and Cadence believe the cooperation will enable customers to incorporate ARM cores into the newly announced Cadence Incisive solution for high-speed verification. Customers thus will be able to build systems with verified, reusable hardware and software IP blocks with greater confidence that the systems will be manufacturable the first time.

"In today's SoC design environment, reusable IP and design tools need to work hand in glove in order to create a design consistency and repeatability in as short a time as possible," said Mike Inglis, executive vice president of marketing at ARM. "It is no longer possible to get premium performance from the latest IP without working with the EDA vendors simultaneously."

The agreement builds on the companies' existing alliance in verification, acceleration/emulation, signal integrity and design services.

Cadence was the first member of Atap, the ARM Technology Access Program, and has delivered more than 30 successful tapeouts of ARM-powered designs through its Design Foundry services business, the companies said. The partners are currently working on improving design chain interoperability via standardized models and validation suites for the ARM Amba bus using the SystemC modeling language.

The companies plan to deliver Cadence Incisive verification tools combined with the ARM Integrator Logic Tile products for acceleration/emulation, along with Cadence signal integrity solutions combined with ARM signal integrity libraries for specific foundries. The results, they said, will benefit architects, hardware verification engineers and software developers, fabless designers, and integrated device manufacturers.

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