With the extension of Actel's digital signal-processing IP offerings, mutual customers now have access to many cost-effective, parameterizable FPGA-based building blocks to speed the development of DSP, multimedia and error-correction applications, the companies said.

Consisting of a convolutional encoder and Viterbi decoder, the Viterbi IP core supports error correction for burst mode and continuous data input. It offers user-configurable parameters, including selectable code rates and interface widths, optional pseudo-bit-error-rate calculation and in-phase detection. The Reed-Solomon encoder and decoder cores, meanwhile, offer full-duplex encoding and decoding.

The companies said the cores are compatible with a variety of international telecom standards, including CCSDS, DECT, ADSL and xDSL. The JPEG encoder and decoder cores also comply with ISO 10918 and provide baseline JPEG compression capabilities, with resolution up to 4,080 x 4,080. They process up to 30 CIF frames per second.

All three cores are offered as encoder-only, decoder-only and encoder-and-decoder configurations. Licenses are available now from 4i2i in either synthesizable RTL or Actel-targeted netlist formats. Prices start at $2,500.

Equipped with two antennas, Innovics' wireless terminals combine two sets of data signals to get the best possible signal. This scheme enables faster processing at the terminal, the company said, thus requiring no modifications to the basestation or network infrastructure. Adding the ARM922T core to the system will enable Innovics to develop power- and performance-sensitive baseband devices, the companies said.

Michael Santarini is senior editor covering electronic design automation for EE Times.