In an indication of the growing importance of reusable intellectual property to fabless chip makers, the Fabless Semiconductor Association (FSA) and the Virtual Socket Interface Alliance (VSIA) announced last week that they have agreed to pool resources to develop and roll out a quality metric for IP cores.

The work will be performed within the VSIA's Development Working Group (DWG) structure. VSIA has had a Quality DWG at work for some time. In August, the group formally announced a metric and procedures for quantifying the quality of a piece of IP.

The metric is based on a checklist of deliverables and attributes. The checklist is used, then multiplied by a list of weights that express the degree of importance a design team attaches to each attribute. Finally, a figure of merit is derived.

VSIA's initial work was intended specifically for soft IP. The agreement will bring FSA's resources into play to work with the VSIA DWG in extending the metric to hard IP.

Vin Ratford, chairman of the FSA's IP Education Working Group, will chair a subgroup within the VSIA DWG to bring this about. Ratford hopes to conclude the effort and announce a metric for hard-IP evaluation within a year.

The efforts represent the first formal cooperation between the two organizations, which have increasingly found themselves trying to help the same member companies with similar challenges like IP reuse, as it becomes a mainstream technique for not only ASIC but also merchant IC design.

Zoran expands MIPS license

Microprocessor core vendor MIPS Technologies Inc. has announced that Zoran Corp. has taken additional licenses for the high-performance MIPS32 4KE cores, and a new license for the 32-bit M4K core.

MIPS Technologies said the new agreements will broaden Zoran's adoption of the MIPS architecture as it continues to develop solutions for high-growth embedded markets.

According to Zoran, the company plans to use the cores for applications in the consumer electronics marketplace.

- Additional reporting by Ron Wilson

Michael Santarini is senior editor covering electronic design automation for EE Times.