Even a lot of the prejudices that guide embedded systems design at the architectural level are preserved in SoC design. Chief among these is the fundamental law of embedded processor selection: Use the same CPU you did last time, unless you are sure it would fail. The accumulated mass of existing code, existing tools and learning curves already climbed weighs just as heavily on the SoC design team as it does on the board-level designer.

All other things being equal, new CPU architectures are only evaluated in start-up design teams, or when a familiar architecture has been pushed far beyond its limits. But there is an important exception to this rule. It occurs in cases where a processor core is being used not to support existing code in the control flow of the application, but rather to replace hard-wired logic in the data flow.

This situation can happen because of a couple of major changes in the processor landscape. First, embedded CPU cores have become very fast: 200-300 MHz is not unheard-of for well implemented cores in 180 nm processes and COT design flows. Second, with the advent of configurable cores that can implement custom instructions, it is possible to greatly accelerate a core on a particular inner loop, nearly matching the performance of dedicated logic. This of course is only applicable to algorithms where most of the time is spent in a few tight inner loops, and where those loops are subject to common acceleration tricks such as single-instruction, multiple-data parallelism.

But these conditions include a large subset of today's embedded computing challenges.So a configurable processor core in an SoC may be used not in place of an off-the-shelf CPU chip, but in place of the dedicated logic or moderate-sized, fast ASIC that went with the CPU chip in a board-level design. In this case, the first commandment to maintain software compatibility is irrelevant. The CPU core has to be evaluated not against the previously-used CPU core, but against an RTL implementation of dedicated hardware.

That makes for a more interesting question. The first-order evaluation will include adequate throughput, die area and energy efficiency. At this level a CPU will almost certainly be inferior to a dedicated solution, but it may be sufficient to meet the system requirements. The second-order questions get more interesting: development time and risk, adaptability to changes in design requirements, testability and maintainability. In these areas the CPU core may pull far ahead of a dedicated design.

One proof of concept is how often configurable CPU cores are used in combination with more conventional CPU cores. According to data from Tensilica, that is a frequent practice. In at least some applications, where the dataflow portion of the design is amenable to extracting parallelism, the new generation of CPU cores, often used in clusters, is proving an interesting alternative to a complex, performance-sensitive RTL design.

Ron Wilson is editorial director of ISD Magazine and a contributor to EE Times. He has covered chip-related matters for 15 years for various industry publications, and was once, in the distant past, a designer himself.