Before the bursting of the bubble, many applications were on a race to higher integration. The driving forces behind the race were at one point rational. If the world was going to need infinite network bandwidth, if media types from web pages to video to virtual reality were going to terminate in shrinking portable devices, and if this wonderful world was going to need infinite on-line storage, then just about every electronic component in the global information space would have to get more integrated, faster and more efficient.

Since then reality has intruded a bit, and design teams now find that they are targeting not enormous gaps opened by infinite demands, but little niches opened by quite temporal circumstance. Not only has the assumption that higher integration is mandatory been undermined, but the means to achieve it have been dissolved as well.

One of the unspoken facts of the bubble days was that the move up the Moore's Law curve was driven by a surplus of venture capital. No matter how much your design capital requirements were, if you had the right buzzwords in your business plan-heck, if you even had a business plan-you were encouraged to take more. So no one balked at pulling together a design team twice the size that anyone in the management had ever managed before, and planning to spend $3-4 million on a system-level chip.

It's not quite like that now. If you aren't self-funded then you'd better have at least one customer ready to make the rounds in Menlo Park with you. And if you are proposing one of those infamous million-dollar mask sets, the customer had better be willing to chip in on the front end.

So design teams are having to rethink the integration question. The first thought for just about everyone is to forget COT design. If you aren't NVidia, nobody's going to pay for it right now.

So what are the alternatives? Well, the FPGA giants will happily assure you that you can go right ahead and do your huge SoC, and just implement it in a huge FPGA. True enough, under some circumstances. But nothing has happened to change the equally huge performance and energy-efficiency penalties that FPGAs cede to cell-based designs. Nor have the heart-stopping piece prices of the largest FPGAs changed much. On a per-gate basis (especially if you let the FPGA vendors count the gates) FPGAs are much cheaper than they used to be. But that doesn't change the sometimes four-digit unit prices for the largest parts.

How about the new generation of macrocell-based ASICs from AMI, Lightspeed, NEC and others? There appears to be some significant leverage over NRE here, but there are also some significant limitations for some types of applications. Perhaps the most obvious of these is the need for the vendor to pre-place memory in the master slice, creating a Procrustean bed in which memory-critical applications may be pained to lie.

So what about the really lame option? You know, the one nobody wants to mention to the VP of Engineering because you know you will end up doing it--lower integration, carefully partition to minimize interchip bandwidths, and make optimum use of existing off-the-shelf parts. Especially now, when it is possible to lean on standard-parts vendors for magical price breaks, this may turn out to be the cheapest solution. And when time to market is often of more strategic importance than density or energy consumption, it may be the best fit to the overall business needs.

It just doesn't look great on a resume.

Ron Wilson is a contributor to EE Times, where he manages the Silicon Engineering section. He has covered chip-related matters for 15 years for various industry publications, and was once, in the distant past, a designer himself.