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EDA Views
EDA vendor representatives tackle controversial and timely issues in these contributed columns.
It's time to move DFT to a higher level (12:00 PM EST, 03/07/05)
Timing models present another standards test (03:05 PM EST, 03/02/05)
Need for debug doesn't stop at first silicon (12:00 PM EST, 02/21/05)
A broader look at ESL design (01:52 PM EST, 02/14/05)
Will China beat the U.S. in verification? (01:36 PM EST, 02/07/05)
Consumer electronics demands new EDA focus (09:20 PM EST, 01/31/05)
Don't pay too much for mixed-signal tools (02:16 PM EST, 01/22/05)
How ESL becomes a business imperative (04:00 PM EST, 01/17/05)
How to boost verification productivity (05:25 PM EST, 01/10/05)
RF ICs: Moore's law on steroids (12:00 PM EST, 01/03/05)
How to select verification IP (12:38 PM EST, 12/28/04)
Why scripts aren't enough for IC design (06:57 PM EST, 12/16/04)
It's time to eliminate wire load models (08:14 PM EST, 12/09/04)
Steps towards a better EDA industry (07:54 PM EST, 12/03/04)
Don't move too quickly to new process nodes (06:02 PM EST, 11/24/04)
Focus on results in system language debate (06:39 PM EST, 11/19/04)
A practical view of ESL design (06:37 PM EST, 11/12/04)
Why full-chip formal verification is possible (01:13 PM EST, 11/08/04)
CCS offers advanced delay calculation methodology (03:00 PM EDT, 10/29/04)
ECSM sets new standard for timing model accuracy (01:14 PM EDT, 10/19/04)
Measuring success before verification is completed (07:00 PM EDT, 10/15/04)
Design complexity drives need for ESL (06:13 PM EDT, 10/08/04)
How to make high-level synthesis work (01:05 PM EDT, 10/04/04)
How FPGAs empower system-level design (05:22 PM EDT, 09/26/04)
Nine reasons to adopt SystemC ESL design (12:58 PM EDT, 09/16/04)
HDL front ends aren't core competency (08:36 PM EDT, 09/09/04)
Analog circuit optimization doesn't replace designers (04:00 PM EDT, 09/06/04)
Why you should outsource IC rule decks (12:00 PM EDT, 08/30/04)
Riding the 'wave' of 90nm signal integrity (03:00 PM EDT, 08/20/04)
'Divide and conquer' with verification IP (03:00 PM EDT, 08/13/04)
Is SystemVerilog the next PL/1? (05:00 PM EDT, 08/06/04)
Advantages of FPGA design methodologies (05:00 PM EDT, 07/30/04)
Put some OOP into your HDL (06:00 PM EDT, 07/21/04)
Optimize drive strengths to reduce power problems (10:00 PM EDT, 07/18/04)
RF EDA moves from niche to mainstream (07:00 PM EDT, 07/09/04)
Getting out of the SoC 'red zone' (08:00 PM EDT, 07/01/04)
ESL 'ecosystem' enables power-efficient ASIPs (02:00 PM EDT, 06/28/04)
Accellera takes new approach to EDA standards (05:00 PM EDT, 06/24/04)
Static verification needs a parallel approach (08:00 PM EDT, 06/15/04)
A new CEO's view of EDA (02:00 PM EDT, 06/04/04)
Accellera reneges on IEEE SystemVerilog transfer (07:00 PM EDT, 06/01/04)
What's needed for mixed-signal verification (06:00 PM EDT, 05/28/04)
A 'network-centric' approach to on-chip interconnect (01:00 PM EDT, 05/21/04)
Top ten attributes of successful RTL hand-off (07:00 PM EDT, 05/14/04)
Lessons learned from 20 years of EDA (05:00 PM EDT, 05/07/04)
Moving from Vera to SystemVerilog 3.1 (12:00 PM EDT, 04/30/04)
A better route to IC closure (05:00 PM EDT, 04/23/04)
Proactive approach needed for verification crisis (07:00 PM EDT, 04/15/04)
Debug-centric verification speeds time to market (06:00 PM EDT, 04/08/04)
Interface-based design sees both forest and trees (08:00 PM EST, 04/02/04)
Chip-level specification needs a new emphasis (07:00 PM EST, 03/26/04)
Spec raises bar for IP and SoC verification (08:00 PM EST, 03/18/04)
Timing constraints should be generated up front (07:00 PM EST, 03/08/04)
Divide-and-conquer kills nanometer designs (06:00 PM EST, 03/04/04)
FPGA, PCB tools must work together (02:00 PM EST, 02/27/04)
Language adoption will drive IC design (01:00 PM EST, 02/23/04)
Semiconductor innovation takes a new direction (01:00 PM EST, 02/13/04)
Design flow integration comes to EDA world (06:00 PM EST, 02/06/04)
Unified co-verification breaks HW/SW bottlenecks (06:00 PM EST, 01/30/04)
Virtual components are more than 'IP' (06:00 PM EST, 01/23/04)
Dirty secrets of derivative SoC design (07:08 PM EST, 01/16/04)
Process automation is key to EDA productivity (06:51 PM EST, 01/09/04)
Evolutionary language fosters a revolution (11:39 AM EST, 01/05/04)
How co-verification speeds firmware development (01:45 PM EST, 12/29/03)
Still plenty of juice at 130-nm node (11:17 AM EST, 12/22/03)
SystemVerilog: Ready, set, code (12:58 PM EST, 12/15/03)
Plan-up front for FPGA debugging (04:53 PM EST, 12/05/03)
RTL timing analysis gets job done (11:08 AM EST, 12/01/03)
A new approach to system-level design (12:33 AM EST, 12/01/03)
Open-source trend a bright light in EDA's future (11:01 AM EST, 11/24/03)
Correct-by-construction becoming design mantra (11:49 AM EST, 11/17/03)
Assertion-based coverage metrics revolutionize verification (09:10 PM EST, 11/07/03)
Process variations require parametric yield enhancement (07:22 PM EST, 10/31/03)
Exploding the 'myths' of standards creation (01:01 PM EST, 10/27/03)
'Virtual platforms' speed automotive design (06:51 PM EDT, 10/17/03)
Bridging the frequency-time domain gap (12:20 PM EDT, 10/10/03)
Debunking the 'urban legends' of DFM (06:20 PM EDT, 10/03/03)
Revolution comes to SoC methods (12:04 PM EDT, 09/29/03)
'Software compiled' methodology is needed for ESL (06:50 PM EDT, 09/18/03)
Stone axes, soldering guns, and SoCs (05:48 PM EDT, 09/12/03)
Move beyond the legacy of IR drop (11:25 AM EDT, 09/08/03)
Why EDA shouldn't ignore FPGAs (12:30 PM EDT, 09/01/03)
RTL design handoff is ready (07:19 PM EDT, 08/22/03)
ESL must keep software in mind (11:11 AM EDT, 08/18/03)
A new vision of silicon compilation (01:18 PM EDT, 08/08/03)
It's time to return to 10x passion (01:49 PM EDT, 07/30/03)
Why we don't have IP quality yet (08:55 PM EDT, 07/24/03)
Consumer electronics drives chip design technology (10:02 PM EDT, 07/18/03)
Electrical wiring design needs EDA support (03:14 PM EDT, 07/14/03)
Improve the library, not the tools, to achieve timing closure (11:16 AM EDT, 07/07/03)
No simple solution to verification problem (01:42 PM EDT, 06/27/03)
EDA business model should be based on tapeout (06:55 PM EDT, 06/20/03)
Reduce test costs throughout the design cycle (07:20 PM EDT, 06/16/03)
Cutting verification costs to one cent (03:17 PM EDT, 06/09/03)
A midyear look at EDA world (11:50 AM EDT, 06/02/03)
Low voltage forces new approach to voltage drop (12:58 PM EDT, 05/27/03)
Behavior-based debug is crucial for verification (08:29 PM EDT, 05/16/03)
Making peace with the timing closure gap (10:46 AM EDT, 05/12/03)
Modules provide alternative to RF SoCs (01:42 PM EDT, 05/05/03)
What's wrong with front-end EDA tools (06:09 PM EDT, 04/25/03)
ASICs won't die, but they will be comatose (08:07 PM EDT, 04/21/03)
SystemVerilog won't cause incompatible standards (02:02 PM EDT, 04/11/03)
Verilog reaches a critical crossroads (07:26 PM EST, 04/04/03)
90 nm requires collaboration on design rules (05:08 PM EST, 03/31/03)
Programmable systems are the next 'killer app' (07:46 PM EST, 03/20/03)
'Fourth generation' simplifies cell characterization (07:30 PM EST, 03/17/03)
The case for SystemC (01:08 PM EST, 03/07/03)
Executable SystemC environment will drive ESL adoption (05:22 PM EST, 03/04/03)
Consumer electronics demands will drive EDA innovation (08:27 PM EST, 02/25/03)
The case for logic BIST (02:05 PM EST, 02/14/03)
S-parameters bridge gap between chips and systems (04:33 PM EST, 02/10/03)
Different platform types are needed for SoC design (07:47 PM EST, 01/31/03)
No, signal integrity is not a solved problem (01:45 PM EST, 01/24/03)
Thinking outside the chip (07:58 PM EST, 01/17/03)
Taking the pain from design for manufacturability (09:02 PM EST, 01/10/03)
Automation makes analog design fun (08:23 PM EST, 01/05/03)
Data management allows collaborative engineering (08:03 PM EST, 12/23/02)
At 90nm, history repeats itself (07:21 PM EST, 12/17/02)
EDA users need unified abstraction level (05:32 PM EST, 12/12/02)
It's hot in here! (05:17 PM EST, 12/03/02)
SoCs need logical virtual prototype (01:20 PM EST, 11/18/02)
Building a verification strategy 'blueprint' (09:13 PM EST, 10/31/02)
Design process management cuts through fear (02:46 PM EDT, 10/25/02)
Assertions aid design-for-verification strategy (02:57 PM EDT, 10/18/02)
Nanometer design requires dynamic analysis (01:57 PM EDT, 10/11/02)
What to do about asynchronous resets (09:58 PM EDT, 09/26/02)
Hardware/software codesign needs new business model (08:21 PM EDT, 09/23/02)
Mixed-signal HDLs put IBIS on steroids (07:28 PM EDT, 09/12/02)
Power problems loom for high-performance SoCs (06:58 PM EDT, 09/05/02)
Strategy for reducing soft errors is needed (01:45 PM EDT, 08/27/02)
Advocates of design languages declare truce (11:53 AM EDT, 08/22/02)
SystemC, Superlog advocates declare truce (05:42 PM EDT, 08/20/02)
EDA can't solve test problems alone (01:42 PM EDT, 08/16/02)
EDA encounters of the Third Kind (07:22 PM EDT, 08/07/02)
Signal integrity moves to front of PCB design flow (01:43 PM EDT, 07/30/02)
Physical synthesis gap bridged slowly (03:00 PM EDT, 07/23/02)
Deep submicron demands 'design integrity' (08:41 PM EDT, 07/12/02)
Hardware emulation for everyone (01:37 PM EDT, 07/08/02)
Under-investment in interoperability is costly (04:35 PM EDT, 06/24/02)
A two-company 'duopoly' won't serve EDA (11:27 PM EDT, 06/13/02)
System-level design brings new methodology (12:51 PM EDT, 06/07/02)
Code generation allows model-based design (02:58 PM EDT, 05/31/02)
Networking and mentoring aid women in engineering (01:29 PM EDT, 05/24/02)
A call for open EDA databases (06:47 PM EDT, 05/16/02)
Royalty-based libraries cost more than you think (01:53 PM EDT, 05/14/02)
Can you afford not to go to DAC? (12:59 PM EDT, 05/08/02)
Communications designers need specialized tools (06:47 PM EDT, 04/26/02)
EDA prepares another abstraction push (07:47 PM EDT, 04/18/02)
EDA prepares another design abstraction push (06:49 PM EDT, 04/16/02)
What's required for golden RTL? (04:38 PM EDT, 04/09/02)
Single tool serves IC verification best (02:33 PM EST, 04/02/02)
Static crosstalk analysis -- a new approach (06:46 PM EST, 03/26/02)
Why PCB design has a great future (12:04 PM EST, 03/15/02)
Unheard-of complexity confronts PCBs (01:12 PM EST, 03/11/02)
High-speed PCBs require a new approach (07:33 PM EST, 03/04/02)
Deep submicron ICs require power signoff (06:33 PM EST, 02/25/02)
X Architecture changeover should be easy (04:14 PM EST, 02/15/02)
Model packaging offers superior protection (01:42 PM EST, 02/06/02)
EDA serves disparate masters (02:26 PM EST, 01/28/02)
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