However, any real engineer who has to get his/her job done in the nanometer silicon era will tell you that the platform is only one piece of the solution. It is the processes that are becoming ever more key to successful design projects. For example, in verification, there is at most a 20% potential productivity improvement by speeding up the platform infrastructure (for example, simulation speed), while there are multiple areas for >10X improvements available from automating the verification process (for example, time to verification closure).

What is the difference between a platform and a process? In the case of SoCs, a design platform is an implementation architecture that can be used as a foundation for rapid design derivatives. It typically consists of a multi-bus (or equivalent) architecture and IP that is tailored for specific classes of target applications. To get the SoC designed in a rapid and predictable timeframe, there must be a well-defined process to define the specs, tailor the platform to support the specs, implement and verify new functions in both hardware and software, and verify that the integrated chip will perform as expected in the system context. In this case, the platform is an enabling foundation, and the process is the means to use the platform effectively to meet your end goals.

Now, let's talk about EDA platforms. An EDA platform is a tools integration architecture that can be used as a foundation for rapid extendibility. It typically consists of a common database (or databases in reality) and a selection of tools that are tailored for specific classes of target applications (simulators, accelerators, and emulators).

To get the design task done in a predictable timeframe, there must be a well defined process. In the case of SoC functional verification, the process starts with the capture of specs in an executable test plan, the development and reuse of multi-level and multi-channel automation rich environments, the inclusion of assertions at both the chip and module levels, and a metric-driven process to rapidly find and fix all bugs and drive towards predictable and measurable verification "closure." Once again, the platform is an enabling foundation, and the process is the means to use the platform effectively to meet your end goals.

How important is this distinction between process and platform? I believe most engineers would tell you that it is critical. I also continue to hear from most managers that they have a huge shortage of expertise needed to design and implement the processes required for designs with ten of millions of gates, regardless of the tools or platforms they get from their EDA suppliers. This is spurring new innovations in how to prepackage advanced process expertise, and automate these processes.

In fact, I've recently become aware of two EDA start-ups who are showing real success in delivering "process automation" solutions for physical implementation and the realization of predictable timing closure. There are others who are totally focused on process automation solutions for functional verification and the realization of predictable and accelerated verification closure.

These companies are drawing many parallels from what companies like Rational did to automate the software engineering processes, leveraging a variety of third party computing, compiler, and debug infrastructures. These new EDA process automation companies leverage the platform infrastructure being integrated by other EDA vendors, but are specialized in prepackaging and codifying deep process expertise for the broader SoC community to readily adopt.

As we evolve into the nanometer era, we'll see a bifurcation in the EDA market between those that are truly experts in CAD algorithms and platform infrastructure, and those that are truly experts in process automation. The process experts will create solutions that enable a broader SoC community to use that infrastructure effectively to achieve end design goals. Although they are a smaller group today, they just may be the key to breaking through the barriers to broader adoption and leverage of next generation silicon technology.

Steve Glaser is vice president of corporate marketing and business development for Verisity Design.