SystemVerilog brings forth a revolution in design and verification. Paradoxically, in part this is because it is an evolutionary language.

SystemVerilog is at the confluence of multiple trends and real-life experiments over the past 10 years, including HDLs, hardware verification languages (HVLs), System C, Superlog and property specification languages. Each one of those strands generated insights through technical and business successes and failures. In parallel, EDA companies learned how end users combine languages and tools within their design and verification flows, and how they complement them with general-purpose languages such as C and Perl.

SystemVerilog came about by honing the design and verification abstractions and constructs coming from all these languages and integrating them in a practical way. It wields revolutionary power precisely because it is a product of evolution and confluence, rather than a mere intellectual exercise in standards.

Specialized tools and languages periodically emerge to better address some new set of specific problems. In the1980s, as schematics became inadequate and synthesis became viable, HDLs such as Verilog and VHDL gained acceptance. In the 1990s, verification became a bottleneck, and HVLs such as Vera and "e" emerged to address that problem. SystemC came about to address system-level issues. Formal techniques have given impetus to property specifications. Each of these tools and languages advanced the state of the art in a specific domain but yielded only point productivity gains.

Moreover, these new languages also created artificial boundaries and barriers that limited the gains. The first such problem is the learning curve: Although most of these languages can be learned in a week, true fluency in their idioms usually takes months. Further, HVLs and HDLs handle some overlapping concepts but use slightly different syntax and semantics.

The patchwork of system-level, coverage, RTL, testbench and property-related tools results in performance loss, unnecessary data shuffling and incompatible application programming interfaces or versions. Verification is still far more time-consuming than design.

SystemVerilog removes those barriers and assembles the pieces needed for design and verification within one language. Further, with one minor exception (a deprecated construct), SystemVerilog is a proper superset of Verilog 2001. Hence, current users of Verilog will have no problem using it. The ability to start from a large installed base, combined with a broad coalition of vendors that are committed to support it, bodes well for SystemVerilog's adoption.

Some key capabilities that distinguish SystemVerilog from Verilog. First, SystemVerilog provides a comprehensive simulation model: It subdivides each time slot into a sequence of 11 phases and specifies what must happen in each such phase. That avoids certain ambiguities and races, which can occur when simulating models that include reactive testbenches, coverage tools and third-party C models interacting with each other. It brings determinism where it's most needed.

Second, features such as those in C++, including structures, classes, C data types, dynamic memory allocation and dynamic processes, make SystemVerilog much more suited for testbench development and for system-level modeling. Third, the same set of assertions can be used by both simulation and static verification tools.

Finally, interfaces have a bigger role in SystemVerilog; they can be separately defined, can include assertions about their behavior and can be reused throughout the design. That yields code that is more compact, more readable and more robust.

There are many other capabilities. For more specifics, see www.accellera.com.

Accellera and its predecessor, Open Verilog International (OVI), led the quick development of the original Verilog and Verilog 2001 and both were later ratified by the IEEE. It's time for the two organizations to team up once again.

A new generation of tools, based on SystemVerilog, will have a revolutionary impact on design and verification.

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