Unlike a digital circuit, which is typically optimized only for speed and power, an analog circuit is designed to meet as many as five to ten performance metrics. As a result, the impact of these process variations is seen as design yield loss, which in turn directly bites the bottom line of the company's profits. This calls for a proactive and a deterministic way to deal with performance and yield, while in the design phase and not after first silicon.

Cost of poor design yield

Design yield, also known as parametric yield, is a design's sensitivity to process variations. In general, designers verify the operation of their circuits at the center point of the process, which is also called the nominal point. In addition, they verify the operation of their circuits at the typical four worst-case "corner" points.

The nominal point is not necessarily "the best operating point for that process", but easiest for fab to control. However, the reality is that with the variations that process parameters exhibit, and the non-linear nature of analog/RF circuits, the design must operate across the entire range of process and operating conditions, and not just the nominal and the four worst-case points. Current tools analyze and optimize a design only for the nominal point without sweeping across the full range of process and operational parameters. A significant part of the loss in yield of a design can be attributed to parametric yield, and it is typically of the order of 20%.

Poor yield can increase the cost of a design by tens of millions of dollars. For example, an industry study of one semiconductor product (Fig 1) shows the need for 10,000 extra wafers over the three-year lifetime of that product because of poor yield. With the average wafer cost at $2,500 per wafer, overall cost of the semiconductor product increases by twenty-five million dollars. The global impact for the semiconductor industry is much more.

Figure 1 -- Impact of parametric yield on a design

Current methods are ineffective for design yield

Simulation and nominal optimization tools analyze a design only for a fixed process point (typically the nominal or supposedly the worst case point). They fall short of optimizing true parametric yield based on process variations. Yield optimization with built-in sensitivity analysis and full knowledge of the distribution of process variations is critical to understanding the factors that contribute to parametric yield, and optimizing the design to achieve the maximum yield!

Built in sensitivity analysis allows the program to determine worst case for environmental factors (such as Vdd and temp) for each point in the process. Then when an optimization is performed at that process point, the appropriate worst case environment is applied. This allows the design to be fully optimized such that the environmental factors will not cause the design to fail. It is critical that such an approach be used during optimization.

It is common to address design yield problems after a design is manufactured. Engineers will track low yielding wafer to see what process variations cause the yield loss. Then they will run simulations to see where the design should be tweaked to improve yield. This is a "redesign by autopsy" approach to addressing design yield issues, and is very costly compared to handling design yield at the front-end of the design process using Design for Yield (DFY) techniques. Use of DFY techniques in the front-end design process will accelerate the design flow and get the final product to market faster and with higher yield.

The impact of the variations in the process parameters and operating conditions to the performance factors of a design is much more for today's nanometer than the sub-micron technologies of the past. Hence, the nominal operating point, which is the center of the distribution of the parameters for a given process, may not be the best operating point for design yield. What is really needed is an automated way to maximize design yield such that the design operates as specified across the entire process and operating environment.

Optimizing design yield

When optimizing an analog/mixed-signal or memory design for multiple performance parameters (Fig. 2), the worst case condition may be different for each performance parameter such as gain, bandwidth, and jitter. Trying to simultaneously optimize a design for each such performance parameter can be a nightmare, and is typically beyond what an individual can assimilate. Furthermore, net yield is determined by the design simultaneously meeting all those requirements. Net yield is always lower than the lowest partial yield (as in Fig 2).

What is really needed is an automated way to maximize the distance between the nominal point of the process and that point in the process where each of the specs for the design begin to fail. This distance is referred to as the "worst-case distance" (Fig 2).

If the design engineer somehow knew what the worst case distance was for each of the performances in the diagram below (and also knew what process parameter caused the failure), then he/she could resize the devices in the design to make it more tolerant of the sensitivity.

Figure 2 -- Optimizing for yield

Having a program that could point out these sensitivities and make suggestions for design improvements would greatly ease the designers' job. Furthermore, if the program could go the last step and make the changes to the design automatically (with the ability to manually intervene at any step,) great improvements in productivity would be accomplished at the same time that yield and performance are improved. "Design For Yield," rather than "Design By Autopsy," holds this promise and needs to be adopted by analog and mixed signal design engineers to reap the benefits.

Ravi K. Ravikumar is vice president of business development at EDA startup ChipMD.