The most costly iteration for standard-cell design is finding a problem after routing, because it requires design changes that necessitate resynthesis. Designers have found that the best way to eliminate design iterations is to make sure the chip is correct by construction at each step of the design flow. The newest design automation tools are moving in this direction, as evidenced by the increased use of physical-synthesis tools, which integrate placement at the register-transfer-level synthesis stage. It is no longer acceptable to synthesize the design incorrectly and fix timing later.

Using synthesis tools to produce the legal placement is less costly and time-consuming than using standalone synthesis and then throwing the design over the wall to a legacy integrated place and route solution. Also, physical synthesis enables designers to select the best routing solution.

More and more, designers are turning to standalone standard-cell routers. A routing engine unbundled from placement concerns can concentrate purely on finding the best possible routing solution. Standalone routers focus on tool performance, design density, timing, signal integrity and manufacturing concerns. A standalone tool also sells for much less than the bundled place and route tools used in legacy design flows. Next-generation routers are being integrated with solutions for checking and improving logic, mask layout, timing, noise, power and yield. In the future, such integration will allow design improvements to be made automatically-by ripping up and rerouting the problem portions of the design.

The goal is a design that is correct when routing is complete. Routing will become the foundation for premanufacturing design tasks, just as physical synthesis is becoming the focal point for implementation tasks (design planning, synthesis, timing budgeting, test insertion, placement). Soon, finding a major problem that requires resynthesis will be history.

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