Contrary to current industry trends, there isn't always a need to migrate to the most advanced process technology. Why? Optimizing at the transistor level increases performance dramatically. A performance increase of more than 70 percent is possible at the 130-nanometer technology node. With the rapid race in the last few years to the most advanced technologies with smaller node sizes, many design teams are leaving significant performance on the table.

New technology nodes have contributed to unstable and complex design rules and ever-increasing fabrication and mask costs. Mask-only costs for a 130-nm design can be $750,000 and up; this figure will exceed $1,000,000 at 90 nm. Newer technologies (90 nm) are moving into mainstream production very slowly. There is a lot of prototyping and validation work going on at 90 nm; very little of this work has resulted in full-scale production.

The result of this slow adoption is higher defect densities and low yields, not to mention the significant challenges associated with signal integrity and power management. The total cost of development for a 90-nm design can reach $10 million, making the technology difficult to access for medium-volume designs.

Clearly, moving to the most advanced process technology can be expensive and very risky. How can these pitfalls be avoided? Can engineers do more to wring more performance out of the current processes and postpone the risk of migration?

How can engineers improve their designs, considering lower levels of abstraction will cause the design team to grow dramatically? As a design team grows, the complexity of managing this type of project will grow as well. Growing a design team will decrease the productivity. And, how many engineers have the knowledge and the experience to implement designs at the transistor level?

With growing design sizes, we normally need to design at a higher level of abstraction. Transistor-level circuit design is becoming a dying art. Hardware engineers are moving toward acquiring software-engineering skills. How can we achieve the all-important transistor-level optimization in this environment?

Companies such as Intel, IBM and AMD are able to cross the 1-GHz barrier with 130-nm technology by using manual transistor-level design optimization. How many ASIC designs have crossed the 1-GHz clock speed barrier? This level of design optimization provides improved chip performance and improved die area as well as lower power consumption due to the reduction in transistor count. Sounds great. So where is the catch?

The solution must be fully automatic tools that can identify the critical paths, redesign the performance bottlenecks at a transistor level and supply all the models we need to verify the design at higher levels of abstraction.

At the block level, we see tools and methodologies that automate design practices that have traditionally been performed manually in order to maximize system performance and minimize silicon area. Specifically, a combination of synthesis, placement and routing, used in conjunction with extraction and analysis, create an effective solution. This approach forms the basis of most ASIC design.

The problem with this method is that it doesn't scale to the transistor level. And it's at the transistor level that we can extract the maximum performance and area efficiency from a given process node. Work at this level has been highly manual. Automation has been nearly nonexistent.

We need a design methodology to gain the benefits of transistor-level design with the ease and predictability of ASIC design. Such a strategy can postpone the risky and expensive move to the next advanced process node.

Automated transistor-level optimization can reduce the overhead burden as well as reduce the size of the design team. Engineers can optimize a design on an ASIC schedule. An increased performance range of 20 to 70 percent is possible. Most importantly, this methodology gains the benefits of the newer technology without taking the risks of migrating to the latest technology.

The pressure to deliver the highest performance at the lowest cost remains the single largest differentiator in achieving a successful product in the market. Moving too quickly to the next process node may not always be the right answer.

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