The chip design process comprises a series of successive refinements and translations that move a design from the conceptual, or abstract, stage to a final, very detailed, device-level implementation. The question of accuracy comes up in almost every discussion with chip designers today. There is no question that accuracy is critical to the success of any new chip design. What's often overlooked is that accuracy is relative: The level of accuracy needed during the final refinement stage of a design may be overkill during the early stages of the design process.

Sharp designers realize that there will always be a trade-off between speed and accuracy and will take advantage of that fact to shorten their design cycles.

To illustrate the point, it may be instructive to draw an analogy to a totally different discipline: fine woodworking. Both are crafts that require a certain level of skill and expertise to achieve excellent results.

As in chip design, a woodworker doesn't start a project by doing the detailed finish work. Instead, the woodworker starts by roughing out the main pieces that will make up the finished project. A certain level of accuracy is important at this stage, but it is much more relaxed than it will be when the final details are added.

For example, it may be perfectly acceptable that the rough shapes are oversized to within a quarter-inch or more of the final dimensions. As the design is refined, the appropriate tools for the finish work are used to add detail and shape the design into the finished product. At these final stages, accuracy becomes extremely important.

The chip design flow follows a similar pattern. Chip designers start out with an idea and the design specification-the raw materials for the project. As in woodworking, the design process starts by roughing out the basic architecture of the design. As the design progresses from basic architecture through the register-transfer level (RTL), a gate-level netlist and finally to a physical layout and tapeout, the team applies different tools to refine and perfect the design. Accuracy becomes more critical as the design moves closer to final tapeout.

So where does the question of accuracy come in? A relatively new tool that is available to designers is the RTL timing analyzer. Unlike gate-level timing analyzers, the RTL timing analyzer generates timing reports directly from RTL code; there is no need to run synthesis first. RTL timing analysis is fast and economical, and it gives RTL designers valuable feedback on their code that can prevent downstream problems during implementation.

The question then arises: How accurate is RTL timing analysis? The simple answer is that it is accurate enough to quickly flag timing issues that would cause problems during the gate-level implementation. Its accuracy can be "close enough" without being "perfect," because the downstream implementation tools are powerful enough to pull a design into timing conformance if the starting point is relatively close.

RTL timing analysis quickly pinpoints paths that exhibit timing behavior that will cause issues during implementation. Using this information, the designer can modify the RTL and quickly reanalyze it for timing conformance before handing off the code for implementation. Design changes at the RTL stage are easier to make, faster and, more important, less costly.

As in our woodworking example, the level of accuracy required depends on where you are in the process. RTL timing analysis gives designers the ability to improve their designs by making an intelligent trade-off between speed and accuracy.

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