As the embedded software increasingly influences the hardware, both hardware and software must be verified together, before the design can be put into silicon. Verifying that the transistor combination is functionality correct is theoretically quadratic to the number of transistors, resulting in a four-fold increase in verification effort every 18 months, greatly exacerbating the problem.

Current HW/SW co-verification methods consist of combining a software simulator/debugger and a hardware simulation tool by means of yet another tool. This approach evolved as a way to bridge two historically separate functions. However, having three tools means having different simulation kernels, which need to communicate with each other. It is cumbersome to establish the interfaces, and once the interfaces are established, a lot of speed is lost in communication overhead.

However, the biggest bottleneck of HW/SW co-verification is the speed of the hardware simulator. Designers have come up with various methods to circumvent this speed constraint, facing trade-offs as they do so. They create a handcrafted C model of the RTL block, which is time consuming and error prone.

They emulate the design in real hardware on an FPGA or an emulation box, which is expensive and cumbersome to achieve the integration with the rest of the HW/SW co-verification environment. Another method is to tweak the testbenches to spend less time on the hardware simulation — however, the simulation is not cycle-accurate any more and might hide undiscovered bugs

There are two critical elements to breaking through today's co-verification speed barrier. First, employ a higher abstraction of the RTL model: cycle-based simulation combined with 2-state logic models can increase the speed of the RTL simulation by a factor of 100x over event driven simulation.

Second, true hardware software co-design can be based on a unified verification system, with one simulation kernel to simulate both the software on the instruction-set simulation (ISS) model and the RTL model of the hardware.

Traditional hardware simulators had their origins in gate-level simulators, which were then extended into the RTL domain. The resulting simulators carry an unnecessary burden of the ability to simulate in picoseconds; yet for RTL verification, cycle-awareness is sufficient. Thus the event-driven simulation kernel can be replaced by a cycle-based simulation kernel.

Additionally, once the reset condition of the design works correctly, the 4-state Verilog or 9-state VHDL logic models are not required any more and can be replaced by a two-state logic model, which only contains the values '1' and '0' and no 'X' or 'Z' anymore.

Note that such two-state logic models require some special precautions to model tri-state logic and need to be able to take certain measures for reading undefined values from a memory or from an external signal. Allowing for this, a cycle-based RTL simulator can run about 100 times faster than the traditional simulators, while still providing full debug capabilities.

As the above solves the hardware simulation speed issue, this leaves the communication issues between the different tools in a HW/SW co-verification environment to be solved. When both the ISS model and the RTL model have the same interface, they can be run with one simulation kernel within one graphical user interface, creating a true unified verification solution for both hardware and embedded software. Such solution really removes the wall between the hardware and software engineers.

A unified co-verification approach is not a significant methodology change for any of the engineers, and is actually easier because the system engineer doesn't have to learn three or four different tools for co-verification, and designers can cross-view elements of both the hardware and software verification.

By taking advantage of abstraction via a unified verification solution with one simulation kernel, using cycle-based simulation for RTL design and a fast ISS, designers can achieve blazingly fast co-verification. The solution can handle any number of instruction set simulators and hardware RTL blocks, and speed increases from 700 to 100,000 cycles per second can be achieved.

The result is that designers can spend less time in building and tweaking testbenches. The testbenches run orders of magnitude faster, so designers can run more of them. The co-design speed bottleneck is removed, improving both designers' time to market silicon and their confidence in first time silicon success.

Cor Schepens is CEO of Adveda B.V., a Netherlands-based EDA startup focusing on hardware/software co-verification.