In one company, the engineers actually announced a successful chip in the company newspaper. It was indeed a proud moment because practically all functional verification and specification compliance was accomplished by building a physical test bench to verify prototypes. Unfortunately, the scrap barrels were full most of the time.

What seemed to be a long, slow movement toward structured and certified RTL design languages represented by Verilog and VHDL were great productivity improvements compared to netlists. However the scrap barrels told a story of chip performance and chip specification continuing to be miles apart.

That was then, and now we are envisioning full systems on chip using enabling semiconductor technology geometries that require expensive tooling. Now silicon tooling is a significant cost factor in chip development. A full scrap barrel here can mean disaster for a systems company. Applying a strictly physical test bench as a verification methodology at this time is about as productive as opening the hood of your car to view the engine when your "check engine" light comes on.

As systems are implemented on silicon at this scale, ever larger pre-designed IP functional blocks help accelerate the overall chip design. However, integration of IP blocks, many of which are purchased externally, is a challenge. Each block has an interface specification that must be verified. A well-designed IP block may function poorly in one SoC, and very well in another — all depending on interpretation of the interface specification.

No wonder that one of the compelling messages at the 2003 DAC was that verification, its methodology, tools and support languages are no longer deemed nice, but essential for success. Similar to many innovations in our industry, issues tend to boil over like soup on a stove prompting direct attention to save the soup.

The specification-interpretation disconnect, that is as old as our industry, is currently being addressed using new system design description languages. Far from a netlist, new concepts are emerging such as Virtual Prototype, ESL, and what I like to call the "executable specification". The goal of an executable specification is to embed the verification of functionality within a description language that is then verified via system tools in a virtual manner.

Wait, I can hear software engineers out there complaining, "I have been telling you that for years. My code listing is the specification!" Not quite. Only when the code contains embedded assertions that can be verified can it add value to determine proper functionality, and identify unspecified behavior. This one concept is a major step forward in our quest to save the soup.

It is not surprising that system level design languages such as System Verilog and System C are being adopted into design flows so rapidly. We are seeing such design languages reach a "ready-enough" condition to be employed at the system level for implementing large SoCs. Sure, the languages are not completely certified yet, but embedded assertion based verification and property specification methodology offer very practical solutions today, resulting in more SoC success.

The stability trade-off is leaning toward Go rather than Wait. This compelling design and verification trend is drawing large groups of engineers to seek a working knowledge of such languages regardless of their state of completion and stability. What? Use a language description before IEEE officially approves it?

Even Accellera, an organization dedicated to speeding up the adoption of new language standards, is finding it hard to stay ahead of system language engineering demand. Engineers seeking hands-on knowledge of such less-than-certified languages are filling seats in any venue where tutorials and other forms of instruction are offered. While no one disputes that knowledge is power, the leading EDA companies realize that this kind of language knowledge dispersion may indeed be a better use of their marketing funds compared to handing out trinkets and T-shirts.

The EDA companies sponsoring regionally scheduled system language-based tutorials are enjoying large turnouts as well as the recognition that comes with sponsoring this kind of event. This also puts significant pressure on the EDA companies to quickly orient their tool support in concert with these languages prompting a win-win situation.

An SoC chip success where the system language concepts are employed provides the best practical push to speed language adoption and certification. No one can really argue with chip success. This adoption speed is being felt throughout the industry so the standards organizations may have somewhat less tolerance for "Let me just make my little point" type discussions, and more of "This language and tool combination actually works so let's move on!"

No doubt, the pressure is on to complete certifications in a timely manner, as it should be, but few seem to be interested in waiting for an official standard to be served up. Soup anyone?

Frank Weiler is president of Apogee Consulting and general chair of the 2004 Design and Verification Conference (DVCon), to be held in San Jose, Calif. March 1-3, 2004.