Complex IC design success cannot be assured by a divide-and-conquer strategy of verifying blocks of a design and then stitching them together without complete full-chip analysis. Designers that mix analog, digital, mixed-signal, and memory blocks, had better abide strictly by the maxim, "the whole is greater than the sum of the parts."

Currently, many companies are still trying to break up a design for verification purposes due to tool capacity and performance limitations. However, the power network and the clock network, which span the entire chip, can each cause changes in the performance of the circuitry within blocks.

Breaking up these networks for analysis eliminates these global effects and can be disastrously insufficient. Only with full-chip transistor level analysis can designers see the actual interactions between blocks and simulate what the final behavior will be in silicon.

One explicit example of how this concept applies is when designers verify design behavior, including the effects of the power network. The power-supply bounce induced by I/Os can feed back through the power network and create noise in the signal path. This effect is invisible to designers unless they simulate the power network across the chip.

Full-chip verification is also essential for accurate timing and power analysis of the clock network. The clock network covers the entire chip, and can involve hundreds of thousands of gates and a much larger number of digital loads as the clock fans out and must arrive with minimal clock skew.

Looking at the network as a whole is the only way for designers to determine the actual timing and loading effects. Clock delay and skew has the potential to slow down critical signal paths, and power spikes through the clock network can cause additional skew and delay.

Capacity and speed limitations have restricted designers from doing full-chip transistor level analysis. Such analysis could take weeks, or be impossible to achieve with traditional tools, so design teams typically try to design around this problem. They make signal interfaces simple — for instance, consciously architecting a design with high-speed serialization versus sending data in parallel to get the signal to arrive correctly.

But that freedom doesn't always exist, such as with array-based designs, especially in memories and imaging electronics/image sensors with peripheral electronics, and designs with complex mixed-signal control loops. SoC design teams use IP from different sources, different geographies and different design generations, including memory, mixed signal and digital elements. Some of the design elements are already characterized, and some are not.

Will the chip work under varying operating conditions when everything is put together? In a real electrical environment, signals are racing back and forth between the design blocks. Designers must thus make the crucial choice between testing each part in an artificial environment, or hooking each part to the rest of the circuit and getting real loads, real interconnect, and real signal delay.

With complex nanometer designs, verification engineers can no longer simply run transistor-level analysis of key parts of the networks, combine the results and hope that the "sum of the parts" is sufficient. The entire design works as an integrated whole and thus must also be analyzed as a whole. Skip this step, and the result may be failed silicon.

Graham Bell is senior director of marketing at Nassda Corporation.