There is another important truth in designing chips today: the time designers have to get product to market is continually shrinking, and the cost of a silicon re-spin before the product is released to the customer is prohibitive. The chip must work right the first time.

Verification crisis looming

Hardware design centers around the world are only now being rudely awakened to this reality. Consider this: a one-million-gate design requires an average of seven experienced verification engineers to ensure a bug-free, robust product. While today's designs easily touch 30 to 40 million gates, there is a verification crisis looming on the horizon. Experts are insisting that design-engineering directors spend what is necessary to lift verification from the bottom of the digital-design-methodology ladder.

Some would argue that verification technology is the most crucial part of the chip design methodology cycle. An increasing number of designers now say that up-front investments in verification is the only way to ensure that a VLSI design project does not eventually go down the drain when the chip does not work. No matter how much money is spent on verification during design, it is minimal when compared to the costs of silicon re-spins.

The price tag for a re-spin can easily reach $1 million, not including the costly delays in getting the product out to the market. If a bug is discovered after the product launch, it could easily cost millions of dollars to the company to recall and replace all the defective chips. Moreover, if customers find too many critical bugs, the chip may have to be totally withdrawn from the market.

Although an endless number of verification tools crowd the market, they are not meant to be a substitute for the innovativeness, creativity, critical thinking skills, and chronic "paranoid" nature of the verification expert. Good verification engineers have to be continuously vigilant. Although they have done everything in their control to find all bugs in the design, they continue reviewing the design until the last nanosecond.

Since the verification team on any project faces the formidable task of ensuring that the design will always work correctly in potentially billions of test cases, there is an acute need for automating the generation and running of test cases, and then quickly comprehending the failures. What's needed are advanced verification techniques such as formal verification, where designs are mathematically checked for correctness without running any tests; equivalence model checking, where you compare against a golden replica of the design; and assertion generation and checking software.

Tools available on demand

Sensing this potentially explosive need for state-of-the-art verification software, companies like IBM have dedicated entire design centers to the development of some of these advanced verification tools. IBM is also one of the first companies to offer verification tools on demand through its e-verification and e-design license strategy.

The verification tools are being offered for licensing on an as-needed basis and can be accessed through a Web portal, under the umbrella of IBM's "e-business on demand" strategy. This helps customers greatly reduce the cost and improve time-to-market.

No chip design group wants to miss a market window because of a bug. Unless the necessary steps are taken to ensure a proactive approach to verification, the quality of our chips will continue to be affected. Verification engineers must be involved in the project right from the product conceptualization stage and the architecture definition stage.

The verification methodology cannot be a hit-or-miss approach. There must be a total verification solution strategy that begins at the time of architecture definition and continues throughout the life of the design cycle of the chip as it grows from block level to system level.

Sunil Kakkar, an engineer with IBM's Engineering & Technology Services team in Bangalore, India, heads the microprocessor and ASIC performance and verification group.