Fixing one violation often causes another, leading to a seemingly endless, unpredictable loop. New design rules and technology challenges now dominate design convergence to the extent that many designers feel IC design has become an unstable, fragile arena.

Gone are the pre-nanometer days of a single-pass place-and-route flow, when a design generally needed only final "cosmetic" corrections to adjust the database to specific design rules. For designs below 130nm, the rules have changed. Signal integrity issues such as cross-talk, noise, and IR-drop are preventing designs from reaching tape-out, leading to a crisis point in product delivery.

With today's typical designs comprising millions of signals, even a fraction of these can result in thousands of violations that cannot be solved manually or in a post-processing patched manner. Even when companies use advanced point tools, many find that their results miss target design goals.

Some companies try to solve the problem through manual iteration of incremental analysis and ECO fixing. Unfortunately, they find such iterations during the post-layout phase typically do not converge predictably, because there are so many unrelated violations. A painful experience results. Companies are forced to compromise on design quality and turn-around time, or else achieve performance and area that are inferior to their design specification.

Although EDA tools are available to analyze designs and identify SI issues, there is no integrated, systematic, and automatic approach to fix the analyzed problems. Therefore, designers resort to a brute-force approach to fix these violations or, alternatively, find themselves with endless manual iterations of the "automatic" flow.

They execute point-tools sequentially, in an attempt to minimize potential signal-integrity and manufacturability problems statistically, but find this multi-stage patch process simply is not working. Even establishing preventive margins at the beginning of the flow, and doing post-processing to try to eliminate remaining violations, falls short. After-the-fact IC implementation simply is not sufficient for nanometer designs because it leaves too many open violations and is too time-consuming.

Market demand for a better solution has driven companies to make acquisitions or try new localized development. However, the real resolution of this issue likely will require an integrated design process that concurrently can build and analyze a design.

Convergence is impacted so greatly by interconnects that a new way of looking at physical design objects is called for. A practical approach would be to replace the simplified flow — physical placement of cells, followed by routing between fixed cells — with one that could modify netlists, make placement adjustments and do detailed routing simultaneously.

Such an approach would need to rely heavily on detailed implementation for critical design decisions, rather than statistical pre-routing and global assumptions. It would need to be able to enhance manufacturability prior to post-processing, to adequately assess the effect of the enhancements on the behavior of the design.

Such an approach could take designs from physical design entry to a clean, routed design that meets all DRC, timing, SI and DFM requirements, yet does not require post-layout iterations. It could prove to be a very attractive solution for advancing companies' product delivery schedules by achieving final closure automatically.

Ultimately, it could lead to a more optimized design in a predictable turn-around time. With nanometer-scale processes, clearly there's a compelling need for such tightly integrated physical design approach to route companies steadfastly toward closure.

Naeem Zafar is president and CEO of Silicon Design Systems, Inc.