Unfortunately, there was considerable fear, uncertainty and doubt (FUD) generated, even to the point of claims being made that there would be two Verilogs as a result. As director of interoperability for Synopsys' Solutions Group, as well as secretary at Accellera, I feel that it is time to explain the reasons and point out the benefits of the transfer. Most importantly, the industry needs to know that the IEEE now has a structure and process that will ensure there will be only one next-generation Verilog language: an effective, single working group.

Recently, a small, but vocal, group of naysayers have postulated that the donation of SystemVerilog to the CAG would cause a split into two Verilog languages. Their fear was that the IEEE 1364 working group, which is responsible for Verilog 2001, and the new IEEE 1800 working group, which will obtain IEEE accreditation for SystemVerilog, would somehow diverge in their work. It is noteworthy that the 1364 committee and Accellera's SystemVerilog committee worked together for more than two years to ensure alignment. Within the IEEE, there is a solid history of different standards working groups interacting and coordinating with each other.

As Accellera stated when SystemVerilog was transferred to the CAG, we were confident that the IEEE would manage the standard effectively. They are doing just that. This week, the IEEE's NesCom and Standards Board have approved the 1800 Project Authorization Request. The new 1800 working group is being formed and its current chair is from a user company, not an EDA company. This in and of itself is evidence of the commitment of the working group to a viable, immediate standard.

Just after the Design Automation Conference, representatives from the IEEE-SA corporate standards program, IEEE CAG, IEEE Design Automation Standards Committee (DASC), and Accellera agreed on a proposal such that, in addition to working on 1800, the new working group will also be responsible for 1364. Sponsorship of this single working group will come jointly from the CAG and the DASC.

The new working group will follow CAG procedures and rules as put forth by the IEEE corporate standards program. The result is a powerful combination of new processes and dedicated companies that will affect a single next-generation IEEE Verilog standard.

Now let's examine the value proposition of the IEEE corporate standards program, the reason why Accellera transferred SystemVerilog to the CAG. Accellera's board is comprised of both user and EDA companies. Interestingly, it was the user companies that made the majority of positive votes for the CAG — as a matter of fact, no user company voted against it.

Various standardization models are used in the EDA industry, and each has its advantages and disadvantages, but the goal of all these methodologies is to get a working, stable standard to the EDA and engineering community. The key is that an association of both EDA vendors and users improve and standardize on a language as quickly as possible and get it out where it will do the most good — on the engineer's workstation.

This is precisely the thinking behind Accellera's move to transfer SystemVerilog 3.1a to the IEEE-SA's CAG. The IEEE's corporate standards program is an extreme makeover of the IEEE standardization process, affording dramatically reduced time-to-market of standards.

According to the timetable presented at this year's Design Automation Conference, the IEEE could have an approved version of SystemVerilog 3.1a available within a year. This is in stark contrast to traditional standardization efforts, which usually take anywhere from three to six years. At the rate that today's silicon complexity is growing, Accellera felt that it was best to get SystemVerilog on a track that was fast, fair and populated by experts from both the EDA vendor and user communities.

The move will also support liaisons with IEEE societies and other IEEE corporate functions and promote corporate representation for the development of the SystemVerilog standard with a "one company, one vote" approach, regardless of the company's size. This will prohibit individual companies from dominating the voting process, and will ensure that the approved version will be available for use in a wide variety of tools and flows. An additional new benefit of the corporate standards program is an expert professional IEEE support staff to ensure that the resulting standard is of the highest quality and will be useful to a broad array of vendors and users.

Though Accellera's transfer of SystemVerilog 3.1a to the IEEE-CAG has generated some controversy, this should now be put behind us. The Accellera board is convinced that the CAG's fair, streamlined, market-relevant approach and single working group for 1800 and 1364 will get one IEEE standard to the EDA and user communities faster than ever before in EDA history.

All parties are in agreement and pulling together in the same direction. The bottom line is that EDA standards must support tool development and advanced IC design, or they have no real value in the market. Getting a stable, robust version of SystemVerilog out to the user community means that engineers can begin the next generation of system-on-chip designs with the languages and tools they need to get their products to market quickly. After all, isn't that what EDA is all about?

Karen Bartleson is director of interoperability at Synopsys, Inc.