The return of the transistor poses dramatic challenges to developers of process technologies, design tools and integrated circuits. Until now, these three communities were able to deliver next generation advances with minimal interference by using successive levels of abstractions effectively.

For nanometer circuits operating at highest performance levels, traditional abstraction boundaries are crumbling. Nanometer design methodologies can no longer abstract away process- and device-level effects. Performance problems are increasingly difficult to patch at the end of the design cycle. Moreover, as market windows continue to shrink, long and laborious circuit simulations are no longer practical.

Chip designers are on the cusp of an infectious disease that can't be cured by current design and verification methods. Chip designs that are 20M, 50M, even 100M gates in size, with multiple functions, and a lot of memory and increasing analog simply won't react to the old "Spice and tweak" routine.

For System on Chip (SoC) designers, the return of the transistor means that the Spice-and-tweak regime is nearing the end of its reign. This practice, which worked just fine for analog design and digital critical paths ten years ago, is not a practical solution as growing portions of system-on-chip (SoC) glow red hot with performance failures.

SoCs, now encompassing tens of millions of gates, are sinkholes for all the components that, in the good old days, were off-chip. Analog functions must now be implemented on-chip for reasons of performance and cost, placing incredible stress on the small community of analog designers using the 1970s Spice-and-tweak methodology.

The analog-in-SoC problem is aggravated by the explosive demand for consumer and communications chips. The result? SoC designers need to find a design and verification methodology that optimizes designs as they design, not correct those designs and try to optimize them after the fact. We've got to get away from what I call the creeping "red zone."

What is this red zone? Back before the advent of commercial EDA tools — and certainly before the use of off-the-shelf IP cores — chip designers used to manually "red flag" design or layout violations. As chip design got more complex, verification software started inserting red flags whenever it detected design or layout problems that would endanger chip or system performance.

However, as we see the next generation of complex, multi-functional, mixed-signal SoCs, we can envision the emergence of a veritable "red zone" — a spreading and all-encompassing carpet of red-flagged verification violations that will prohibit the manufacture of chips needed for high-demand consumer (and other) products.

Why do we find ourselves up against this design-fatal red zone? Today, analog transistors account for merely 2% of the SoC transistors. But it's 20% of the area, and it is the reason for 50% of the respins, which means market window misses and, given nanometer mask costs, excessive cost overruns.

As we move down to 90nm and then 65nm, the red zone is quickly spreading fast beyond analog. DSM interconnect effects are compounded by the fact that it is increasingly difficult to maintain the tidy digital abstraction of transistors.

SoC design methodologies that try to take account of this unruly behavior at the front end of the design cycle are not able to deliver on the promise because, more often than not, these behavioral problems are only apparent at the tail end of physical design. If we do not have enough time and expertise to cure analog-in-SoC problems using Spice-and-tweak, what are we going to do when digital turns into analog in SoC?

Red on departure is dead on arrival! As the red zone spreads, design tools will have to punch through the gate level abstraction down to the transistor level throughout the design cycle. Circuit and layout design tools will have to incorporate synthesis techniques that reach beyond the gate level abstraction to optimize the transistor. In fact, nanometer design methodology will only be effective when design tools incorporate the type of knowledge that is held in the brains of analog design engineers.

These optimization techniques will be vastly different than Spice because Spice is merely a validation tool that requires an expert designer to take action. Built-in transistor optimization will be based on automatic synthesis, rather than human intervention. It will also require that analog design knowledge be captured in device, circuit and system libraries that will be available to the synthesis and optimization tools.

Only when we have a nanometer design methodology that can deal with the return of the transistor will we be able to contain and shrink the red zone. As in the 1970s, developers of process technologies, design tools and integrated circuits must collaborate to develop new methodologies for designing ever-faster circuits with ever-finer features. Alone, none of these communities can get rid of the red.

Ariel Sella is CEO of analog tools provider Barcelona Design.