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Put some OOP into your HDL
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A lot of effort is going into creating the next generation HDL languages beyond Verilog and VHDL. The two languages that have taken the lead are SystemC and SystemVerilog.

SystemC adds a library on top of C/C++ that makes it an HDL, but at a higher level. SystemVerilog has lots of new features added to it that make it very enhanced and powerful.

So what do both these languages have in common that we all need to think about?

OOP!

No, I didn't fall or mistype or drop my drinking glass.

I am talking about Object Oriented Programming, or OOP. Some of you already know about this. OOP is no longer the domain of software engineers; it's for the rest of us now.

Why is OOP the next big thing? Because, first of all, both SystemC and SystemVerilog both support it. But the other big reason is that if we don't use it, the industry will get bogged down.

Now that might seem like a big statement for me to say, but hear me out. We all know that ASICs and FPGAs continue to get bigger. A design with over a dozen million gates is almost the norm. Imagine the huge amount of code that needs to be written! So big are these designs that the term SOC has been around for awhile. So how does one deal with such huge amounts of code?

Well, we could write the HDL code a lot cleaner and neater, but we all know that most engineers have a tight schedule and lots of other things to do. So they just throw the code together, and then tweak the hell out of it to get it to work.

Enter OOP.

OOP forces engineers to write code in a more organized and better structured manner. But what is even more important is that OOP's main purpose is to provide maintainability. In other words, should changes or improvements or updates be done, a process is provided where this can be done smoothly and properly.

So what's the big deal about maintainability?

In many of the projects I have been on, the code gets so big that when changes are made later in the project, the code breaks easily. A lot of time is wasted just trying to get the design working again, much less get the original change working. Now, some engineers say this is a symptom of poor coding and design. That may be true, but this is happening an awful lot, and with big designs, it's only going to get worse!

The other issue it design reuse. There are standards and processes to deal with some of this, but all too often, engineers just take an existing design from a previous project, and hack it to death so that it will work for the next project. By the time that design is ready for the third generation, you have a hack on top of a hack to work with. This is how some spaghetti code gets created.

OOP is especially created to deal with this kind of a situation. Changes and updates can be done painlessly and easily, without breaking or damaging the original functionality of the design. This saves lot of time, money and headaches.

Even better, with OOP, one can use the design as a base for building other designs on top of it. This can be very useful. Instead of putting various IP blocks together to form a design, use OOP as a foundation platform. This has always been a dream for many companies and engineers. But using an existing design has been so painful, it was often better just to start from scratch.

OOP for all!

Ronald Goodstein is president of First Shot Logic Simulation and Design. He can be reached at rongood@world.std.com or 617-734-1409.





The views and opinions expressed in this column are strictly those of the author and should not be taken as an editorial position of EE Times or any of its other editors, publications or Web sites.


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