But it's more than that. If we're going to make the proverbial leap to 90nm, 65nm and below with any success, we absolutely must find new core technologies for new tools that will span greater ranges of component performance while delivering much greater accuracy for unified system-level team use. And we have to stop working as isolated IC, packaging, or PCB designers and start working as system-level teams.

Take the case of signal integrity for high-frequency nanometer designs. 3GHz, 130nm designs (with up to 2 GHz I/O speeds) are giving us barely-acceptable yields. But at 90nm, high-performance devices will achieve internal speeds as high as 5 GHz and I/O speeds as high as 3 GHz, and we'll see more and more parasitic problems in the package and the interconnects to the IC.

Designers will require tools that can more accurately verify signal propagation, power integration, IR drop, and AC ground bounce — issues that will all become bigger hurdles at 90nm and below. What do we need to change?

First and foremost, we have to stop looking at the signal integrity of each separate component, and start looking at the interconnects in between. These interconnects are where we will encounter more and more signal integrity problems as we move to higher-frequency, lower-nanometer designs.

That means that design teams working on various components must start talking to each another. The industry has tried to move in this direction before, but now we are to the point where the situation is crucial. We have to see end-product design managers requiring their component design groups to develop processes such as IC/packaging co-design.

Right now, designers use quasi-static resistance and capacitance (RC) extraction tools to verify and analyze various electrical effect problems. These tools were designed to handle 0.25 micron designs, and they still worked pretty well at 0.18 microns. For 130nm design applicability, tool developers added inductance (L) to the parasitic extraction.

To efficiently perform full-chip or critical-net RLC extraction, such numerical techniques as finite-element or boundary-element methods cannot be applied directly. Instead, a model-based solution has been used in commercial tools where a model library of various layout patterns is pre-characterized, and the final Spice netlists are obtained by stitching and reducing the models of matched patterns.

Clearly, the traditional quasi-static technology has to move to another core technology base. While RLC extraction is fine for low-frequency designs, say below 500MHz, what are designers supposed to do when they get 5 GHz designs from their managers? To correctly analyze the signal behaviors from DC to 15 GHz (such as 3x harmonics of 5 GHz designs), including the effect of lossy substrates, a full-wave field solver will need to be used.

Signal integrity engineers have traditionally used 3D full-wave field solvers to analyze signal traces and power/ground planes in high-frequency package and PCB designs. These 3D full-wave field solvers, however, can only handle small geometries and take long time to run. In addition, they are hard to use, and their results, in the form of S parameters, are hard to understand.

For circuit designers to routinely perform on-chip full-wave extraction, and to extend the extraction beyond the cell levels to the critical nets, power distribution, and even full chip, an efficient model-based full-wave solution becomes a natural choice. The S parameters of individual patterns can be combined, and wide-bandwidth Spice models are derived through curve-fitting the S parameters over a wide frequency range.

Such model-based full-wave solutions can, in fact, be applied to the package and PCB extractions as well. For IC-package/PCB co-design to become a reality at high frequencies, it is a must to have efficient full-wave extraction for complex structures, and an efficient model-based solution is absolutely crucial.

For high-frequency nanometer electrical effects tools to pull their weight in the oncoming design era — where momentous changes in the physics of the chip are already starting to impede timely and efficient electronic end-product development — we need to see a real technological revolution within the next 12 months. We have to work from a system-level perspective.

Otherwise, those technical issues that crop up in between components will result in wholesale end-product failure. And we need to see EDA industry-wide adoption of new core technologies on which EDA tools, especially signal integrity tools, will be based. The EDA world can no longer afford to force-fit old tool technology into new types of high-frequency designs.

Ching-Chao Huang is senior vice president of Optimal Corp. (San Jose, Calif.).