These newly introduced products take one of two approaches. The first is based on behavioral synthesis, which has been tried several times with limited success. While there may have been some advances in behavioral synthesis technology, the focus today seems to be one of reducing the scope to simple accelerators, and constraining the input code to contain the limitations of behavioral synthesis. This approach may make it possible to achieve acceptable design results.

The second approach is based on optimized architecture synthesis. This combines the notion of design-time configurable IP for processors and accelerators, along with design exploration and configuration tools to configure the IP from C applications.

This approach is genuinely new. It offers the promise of being able to create complete application engines such as an H.264 video codec or a CDMA modem—engines that are completely beyond the scope of traditional behavioral synthesis technology.

The use of design-time configurable IP eliminates the problem of scope. The use of design-time configurable IP effectively addresses several major design challenges such as verification, system-on-chip (SoC) integration, software integration, and timing and physical closure.

There are three main goals in deploying high-level synthesis, whether it is behavioral or optimized architecture:

First is reducing the time it takes to go from functional specification to verified RTL while also accounting for timing and physical closure. If timing and closure are not considered, there's the risk that a designer reduces design capture time, only to extend the time it takes to verify the design and complete timing and physical closure.

Next, explore alternative implementations to make trade-offs in area, performance, and power. If there is a simple performance area/performance target, synthesized designs must equal or beat hand-coded RTL.

Finally, enable C code reuse for different area/performance designs. RTL has an implied micro-architecture that makes it impossible to re-use at significantly different points of area or performance.

There are additional considerations for the successful introduction of high-level synthesis into existing SoC design flows and SoC structures. One is to ensure that high-level synthesis really works.

Another is learning how to integrate synthesized blocks from C with legacy RTL blocks. Then there is the issue of integrating high-level synthesis with the existing tool flow, and finally, how to use high-level synthesis without putting existing projects at risk.

Here is where an investigation and deployment roadmap can help. The roadmap has four steps, the first of which is a technology/product introduction and benchmark. This step determines if it's worth investigating the technology any further. Key considerations are how long it will take to complete the benchmark; the number and complexity of changes to the original C code required; and the quality of results.

Second is a technology/roadmap review. It's important to understand the technology's capabilities and how they work. High-level synthesis is in its infancy, and it should have a roadmap that offers much more than today's accelerator capability.

The third consideration is the deployment methodology, that is, how high-level synthesis fits into existing design flows and interacts with legacy RTL, and how the technology be implemented in a controlled manner. Finally, consider the factors involved in low-risk deployment. Wide adoption requires an approach that allows virtually risk-free learning and deployment of the technology.

Moore's law enables designers to integrate more and more in a single device. For more than a decade, the semiconductor industry has been struggling with this increasing complexity without a significant productivity boost. High-level synthesis provides the most promise for significant IC design productivity benefits.

Consider performing a comparative evaluation of behavioral synthesis and optimized architecture synthesis. This will show which is the new and productive technology that will finally solve a chronic design problem.

Vinod Kathail is founder, CTO, and vice president of engineering at Synfora Inc.