Static timing analysis and timing-driven optimization tools require highly accurate and efficient delay calculation. Transistor drive capability and input capacitance are becoming more complex and non-linear at 90 nanometers and below.

Computing the response of a standard cell and the interconnect it drives is challenging, particularly for highly resistive nets, such as top-level routes. In addition, delay and slew of signals are dependent on many variables. For example, voltage drop from non-ideal power networks can degrade performance significantly.

Integrated circuit designers are increasingly concerned with power issues. Lower Vdd values and multiple voltage regions are used to reduce dynamic power. Libraries and electronic design automation (EDA) tools must support accurate delay calculation for the complex circuits seen in power-aware designs.

Power calculation itself requires very accurate information about timing, including switching windows and signal slew times. Advanced driver and receiver modeling are needed to generate this delay and slew data.

Similarly, signal integrity analysis is inter-dependent with static timing analysis and delay calculation. Non-linear current source modeling enables significantly better quality of results for signal integrity analysis. Synopsys' Composite Current Source (CCS) delay calculation technology directly addresses all of the critical requirements for nanometer delay calculation. The CCS technology includes an advanced current-based driver model and a comprehensive receiver model to provide highly accurate delay calculation and signal integrity analysis.

The driver model defines how the cell will source current to an arbitrary distributed resistor and capacitor network. CCS uses a time-varying, voltage-dependent non-linear current source to represent the drive capability of a cell. The receiver model represents the capacitance of a cell input pin. The CCS receiver model describes how the capacitance can vary due to factors including input slew and output load. It is a two-part representation, with dynamic adjustment of the capacitance during the transition.

This provides high accuracy for cells, including those with a very large Miller effect. The resulting measurements of slew and delay are typically within two percent of Hspice.

CCS provides accurate driver and receiver models

Key advantages of CCS include:

• Accurate driver and receiver modeling of nanometer timing, including voltage and temperature variation.
• Easy characterization with HSpice current solutions.
• Extensible, scalable for statistical timing analysis and optimization.

CCS builds on the comprehensive library modeling capabilities of Liberty. It supports high accuracy with a modest amount of additional data. Characterization for CCS is very straightforward.

The library data is easily generated from HSpice measurements, leveraging the same transient simulations used in existing library characterization flows. Customers are reporting that CCS provides clear advantages over other approaches: reduced design margins, high accuracy compared to circuit simulation, and low characterization overhead.

CCS is a foundation technology for Synopsys that is being deployed throughout the Synopsys Galaxy Design Platform to improve quality of results and to reduce turnaround time.

CCS today delivers accurate modeling and delay calculation to address sub-90 nm static timing, signal integrity, and low power design challenges, and it is scalable for future requirements, such as statistical design.

Bill Mullen is Group Director of R&D for Synopsys static timing and signal integrity analysis products. Rajiv Maheshwary is senior director of marketing at Synopsys, responsible for Synopsys sign-off products.