For this reason, and others, an alternative to WLMs is clearly needed. The EDA industry's first attempt at this was physical synthesis. The idea there was to get from RTL to gates, somehow, then to place the gates and incrementally fix the logic structure using the improved interconnect estimation afforded by gate placement information.

Of course, these tools were really just placement tools in disguise. They had RTL input capability that no one uses, and they can perform some very limited restructuring of the logic. They did not better address the process of modeling interconnect for the process of creating the global logic structure from the RTL starting point.

The patchwork of fixes left behind by the application of solely local transformations leads to design topologies with notoriously bad behavior in terms of congestion and noise and signal integrity problems. Coupled with the use model, data requirements and necessary knowledge, physical synthesis has not been widely embraced by synthesis users. On the contrary, despite the accuracy and predictability issues of WLMs, synthesis users have chosen them over the adoption of the physical synthesis alternative.

Somewhere, there must be a solution that works for the front-end designer. The question of interconnect modeling for the RTL to gates process still needs an answer. How can interconnect be modeled such that the resulting use model is digestible by front-end designers, while still yielding a high enough signal-to-noise ratio to guide the creation of a physically attractive global logic topology?

The answer should be framed within the context of the established evolutionary trajectory of system-on-chip (SoC) design. There are a couple of overwhelming, interrelated trends that have been well documented and are imminently relevant.

The first trend is the growing number of macros (memories, processors, analog blocks, IP) on an SoC. Today's average of 50 or so macros will shortly grow to over 100, and that trend shows every indication of continuing. The related second trend is toward a higher degree of common (or reused) functionality. This is because reusable blocks are often captured in macro form, hence the interrelationship.

These trends are pertinent in the elimination of WLMs because they have such a profound effect of the physical realization that the WLMs were seeking to predict. Statistics for a process node do not suffice when the realization is dominated and driven by the very design specific use of a large number of macros. That is, the accuracy of WLMs can be expected to get worse not just because of process modeling, but because of the changing nature of the designs themselves.

The solution to the designer's interconnect modeling quandary, therefore, needs to incorporate both process modeling and design-specific aspects in a manner to provide a high enough level of accuracy to drive optimization. The crux of the accuracy issue for optimization is providing a trade-off between the magnitude of a design change and the ability to determine whether or not the change improves the design.

For example, small, local changes such as gate sizing require a higher level of accuracy than architecture selection for an adder. If the optimization strategy can perform a majority of its work on more global transformations, it will have less sensitive modeling accuracy. It has been shown that global optimization techniques have extended the useful life of WLMs, but this has not eliminated the need for change. For the front-end designer, the elimination of WLMs will come with the use of a combination of improved process and design-specific modeling in conjunction with global optimization technology. This combination is the only way to provide an accuracy level high enough to achieve the best optimization results without encumbering the designer with the responsibility of detailed aspects of physical implementation.

A new generation of interconnect modeling is long overdue. The high hopes of physical synthesis as the answer have not been met. All indications are that there are solutions possible that address the signal-to-noise ratio problem in a manner that will be favorably viewed by the front-end designer.

Chi-Ping Hsu is corporate vice president for new synthesis at Cadence Design Systems.