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How to select verification IP
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EEdesign.com


I met recently with a customer who told me, "Verification IP (VIP) will make you successful — or kill you."

He went on to tell me that due diligence in picking a VIP vendor is as important as in picking a vendor for tools. Our experience is that not enough companies take the VIP vendor selection process seriously enough and that many pay for this with either late ICs, functional bugs, or both.

A recent survey of designers by John Cooley confirms that not enough VIP vendors take this seriously enough, either.

Much like designers have used silicon IP to rapidly build SoCs, designers are using Verification IP, especially for standard interface protocols, to assemble entire verification environments. Certainly, then, one of the first things designers look for in their potential vendors is an in-depth knowledge of the relevant protocol specifications.

Interface protocols are increasingly complex and require deep, protocol-specific knowledge. PCI Express epitomizes the new level of protocol complexity as it is a highly scalable, switch-based, packetized protocol, and is configurable to address a wide variety of applications.

While essential, protocol knowledge is only the tip of the vendor selection iceberg. A vendor's VIP portfolio, quality, design process and expert technical support are the elements that are sometimes missed and end up sinking chips (pun intended).

In a recent worldwide survey of designers, verification engineers, and design managers, one quarter of those surveyed indicated they have more than six IP blocks in their designs, so it's essential that a VIP vendor offer a broad portfolio. While many buyers think of the potential economic advantage — and there is a financial gain from buying multiple titles from a single vendor — there are other significant advantages.

Obtaining a portfolio of VIP from a single vendor allows you to have a consistent usage model, interface style and control method that allows designers to build a testbench rapidly. For example, VIP should offer testbench-wide control of messages and logging, which is required to handle the data that is generated from all of the VIP in a complex SoC verification environment.

While a large portfolio of VIP offers many advantages, the only thing worse than purchasing a low quality piece of VIP is buying a whole portfolio of poor quality VIP. A good indicator of VIP quality is the number of designs in silicon that have been verified using the VIP — designers should ask about this.

Another highly effective, but simple step that designers should take is to examine the quality metrics since the first release of a VIP product and find out how often new versions have been released. If you need a standard that is relatively new to the market, such as PCI Express or AMBA AXI, you need to check that the initial quality, the quality level of the first few releases, is solid.

A new release every week (or more often) means you are paying your VIP vendor to be their quality assurance department and your chip has become the test fixture. It is important not to confuse this kind of "vendor responsiveness" with quality. VIP vendor responsiveness should be assessed based on the vendor's ability to answer the difficult usage and protocol questions, not the ability to deliver weekly bug fix releases due to low product quality. Run, don't walk, from the release-of-the-week club.

Inspecting the quality of individual IP blocks is one thing, but it's even more important to assess your vendor and their design processes. One of the simplest and most effective steps that you can take is to examine their test plans. You should be able to trace from the industry specification, through the functional specification, to the test plan for each and every item in the industry specification.

This means that the test plan will be a significant document. For example, the Synopsys DesignWare PCI Express test plan is a 101 page document that details each element of the plan to verify the VIP against the industry specification. In addition to directed testing, constrained random testing is critical to generating enough interface traffic to ensure coverage as well as finding deep, dark corner case conditions that nearly impossible to conceive and are therefore not explicit in the test plan.

Finally, designers need to ensure that their VIP vendor can support them at the critical time they need it, like tape-out. This means that the vendor must have the extensive, expert resources necessary to handle this support, as well as a proven track record of delivering it.

There's no question that designers are requiring increasing amounts of Verification IP and that this trend is only expected to continue. However, if designers don't take it upon themselves to examine their VIP vendor as seriously as they do their silicon IP or design tools, the VIP they acquire may end up hurting them more than it helps.

Ed Bard is director of marketing for DesignWare IP libraries at Synopsys.





The views and opinions expressed in this column are strictly those of the author and should not be taken as an editorial position of EE Times or any of its other editors, publications or Web sites.


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