So is wireless chip design getting easier? Emphatically no. Design teams are faced with the challenge of maintaining a frantic pace through the design and verification phase for months and even years, only to realize another re-spin is required to get to production silicon.

My friends in the investment community claim that nearly 50 percent of the high-frequency startups in the U.S. have gone under in the last three years. Most casualties underestimated the difficulty of getting wireless products production worthy in a timely fashion.

While the digital world raced by with shrinking geometries, increasing clock speeds and constantly growing transistor counts, the RF world sat by with three- transistor GaAs power amplifiers sitting on boards filled with discrete filters, bipolar switching and CMOS control logic. All this was in a metal can package, nicely shielded and completely separate from the rest of the transmitter and receiver sections and, of course, totally separate from the evil digital baseband section.

Enter Bluetooth, WiFi and 3G. How do we get transceivers for high volume products that cost $1 to $2? This has driven the industry's move to SiGe and RF CMOS for advanced RF IC products. So Moore's law, which sat mostly dormant in the RF and microwave space for nearly 20 years, has seen a nearly step-function response in the last few years of RF IC design.

Transceivers have grown in five years from maybe a hundred transistors to tens of thousands, and the move from GaAs to silicon has added the complexity of parasitic layout elements to the tune of hundreds of thousands of extracted resistors, capacitors and inductors for current state-of-the-art designs. This is all further complicated by a dirty noise environmentt and by the fact that each new wireless standard has less noise headroom and all types of blocking signals to deal with.

The design challenges associated with current RF IC design have strained the traditional time-domain and frequency-domain simulators that have evolved from the microwave and RF board-level design environments. The Spice based time-domain tools really struggle with high frequency and large designs and fall flat with digital modulation and multi-tone analysis.

This is further complicated when there is a large difference between RF and IF (intermediate frequency) such as occurs in low-IF designs. The harmonic balance tools were developed for board level and GaAs MMIC designs and do not have the capacity or the capability to simulate today's radios. In most cases they can only simulate individual blocks of a receive (Rx) or transmit (Tx) chain with sinusoidal inputs.

I have personally visited over 90 percent of the top 30 worldwide RF IC suppliers. The average number of spins of silicon to working silicon, once they have the foundry model situation well in hand, is four to five.

Those that are doing fewer successfully, in addition to probably being really good, are paying either a design time penalty — they brute-force simulate for several extra months — or are paying a technology penalty. They may be using an older process, settling for lower levels of integration or building a module, and paying a system performance and cost penalty.

Designers are wonderful at working around the limitations of their design tools. Today we see Tx and Rx chains being estimated by non-extracted simulations of each block of the chain using simple sinusoidal inputs, measuring IP-3 or even worse IP-2 without taking into account how each block impacts the other. What is really needed is transistor level accurate simulation of a fully parasitic extracted Tx chain using a CDMA modulation to drive it and measure Adjacent Channel Power Ration (ACPR) or Error Vector Magnitude (EVM).

So what is needed for first-time-right RF IC? You need to start with very good experienced designers. As one customer mentioned, "If you hire apes it does not matter what tools you give them."

Good foundry device models are a necessity. Some of the better foundries seem to have a good handle on this but many design organizations are being forced to develop their own model expertise to be successful. The third leg of the success triangle is RF IC verification through simulation. Improving the capability of simulation technology for RF IC design is a problem to which there are tangible solutions.

Having spent more that seven years analyzing the problems associated with modern RF IC design we have identified four focus areas for improving the RF IC design flow.

The advanced RF IC simulator needs to be well integrated into a stable design platform that is well recognized and accepted by designers. The Cadence Analog Design Environment is the clear favorite amongst transceivers designers worldwide. Complete integration involves everything from native support for the Spectre model library to full test bench support.

Next, simulator capacity needs to be large enough to converge on Tx and Rx chains in excess of ten thousand transistors to prevent the need to break up designs into small blocks for simulation, thus sacrificing accuracy. Thirdly, simulation run times need to be extremely fast so designers can do hundreds of simulations in a day to verify functionality and optimization.

Finally, the designer must have the ability to accurately execute advanced analyses at the transistor level using real-world input modulations to ensure confidence prior to tape out.

After a long period of dormancy, Moore's Law is taking hold of the wireless chip market. As always, the EDA industry is ready to respond to facilitate the design tool improvements required to maintain the rapid market growth in wireless products.

Pete Rodriguez is President and CEO of Xpedion Design Systems, Inc.