Addressing these issues will require a significant change in cell modeling standards and characterization techniques, which in itself presents an enormous challenge. Even more political than a presidential election, the fight-for-standards have historically confounded both EDA companies and customers alike. Even though the users' popular vote defines de-facto standards, the "electoral college" from the EDA companies still weigh heavily in the standards process.

Total timing delay is made up of two parts, cell delay and wire delay. Although they are coupled, from a modeling perspective wires can be viewed as delay elements, and the delay through them is more or less independent of the cell driver model (a second order effect at best). Unlike cell delays, which depend on the shape of the waveform supplied by the driver that exhibits itself by the slope dependence of delay, wire delays are pretty much insensitive to the driver.

In the case of transistor circuits, the resistance of the input stage of the gate is modulated by the driver. There are no similar mechanisms for resistive wires. Still, the largest modeling impact of the distributed resistance and capacitance of the interconnect wire is on the cell driving the wire.

Because of changes in the effective load, interconnect changes the delay of its driver cell. The effect of the interconnect wire at the receiver end is the degradation of rise/fall times. The change of input slope impacts the delay through the receiver cell.

How well these effects are captured by different delay calculation methods is the real test of accuracy. All models should be verified by independent means, and verification should be part of regular design flow. Models should pass both cell and wire delay accuracy expectations.

For cell characterization and modeling, the Synopsys Liberty library format has long been the standard depository of timing and power information. Liberty today claims support by more than 100 semiconductor vendors, more than 750 sub-micron libraries, and 30 plus EDA vendors with over 75 production tools. It is remarkable that after 13 years Liberty is still the most popular delay modeling format in use today, which clearly illustrates the absolute power of an industry standard.

In order to better address the nanometer modeling challenges, Synopsys announced the Composite Current Source Model (CCS) standard, which directly competes with the Effective Current Source Model (ECSM) standard authored by Cadence Design Systems and backed by Magma Design Automation. The data representation for CCS has been incorporated into the Synopsys' Liberty open library standard.

The open source license for Liberty is free and readily available to all through the Synopsys TAP-in program. The competing ECSM is a Cadence proprietary format, but has been made available to Magma and Synopsys for integration and support.

So yet another standards battle begins, which reminds me of the great operating system battle of the 1990's — the AT&T System V consortium versus the UNIX BSD group. Millions of dollars were spent, many jobs were lost, and little was accomplished. Until that is, by popular vote, the independent candidate Linux was established as the defacto open source standard.

As a registered EDA independent, my vote today is that the accuracy of the results should be the primary criteria from a user's perspective, rather than who backs a given standard. More important than the simple fight for the data format is the way that data is being used. The process through which the conclusions and decisions are made based on that data needs to be robust and reliable.

Therefore, it is essential that the formats be freely available. Independent tests of the accuracy of delay calculations using the different formats should be part of every design and verification flow.

Dan Nenni is a 20 year EDA veteran and is currently a sales and marketing consultant (dnenni@yahoo.com).