I chuckled to myself when I read the closing of Greg Mokler's review of the Verisity Users Group meeting in ESNUG 350. Greg works at TI in Dallas and he wrote: "One of the users in the audience asked Janick Bergeron why he recommended [Synopsys'] Vera over [Verisity's] Specman at the last meeting of SNUG. We all wanted to hear his answer, but never got one."

Why did I laugh? Because Janick is a consultant, as I am. We sell our time to the highest bidder. And taking the wrong side in a controversy can reduce the number of bidders wanting your time. (The last known Dataquest data gave Specman 77 percent market share vs. Vera's 19 percent. But there's the Million Man Synopsys Sales Machine pushing Vera going against a half a dozen Verisity-ites pushing Specman, so who will win this little EDA brush war is still very much up for debate.) Janick was in the hot seat.

Sure enough, Janick quickly replied. "I never stated such a thing during my SNUG presentation," wrote Janick. "My explicit statement was that I preferred Vera over VHDL and Verilog. I also prefer Specman over VHDL and Verilog. By my estimates, I'm over 5x more efficient writing testbenches in either language." Janick went on for six paragraphs.

"I could produce a comparative table of various features in each language (e.g. temporals in Specman, stream generator in Vera) but that would not convey how these languages are useful. Language features is but one element in the selection process. You have to look at your training costs, existing expertise, business relationship, license costs, access to third-party support, integration with existing models, etc.," continued Janick. "The opportunity that Vera and Specman offer is to break away from the bad habits, low-level approaches, and ad-hoc verification processes most commonly used with VHDL and Verilog."

"It is not my role to make a language choice on behalf of those evaluating them," concluded Janick. "In my personal experience, Vera and Specman both offer tremendous productivity gains over VHDL and Verilog for verification."

Janick's run for cover may be moot. A few months ago, Tom Faison of Nortel accidentally foreshadowed this in an e-mail. "Right now, there's no real meat to SystemC, and yet we have to be planning NOW for the next-generation verification methodology. So SystemC is a sword of Damocles which will chop off any residual interest in dedicated verification languages like Specman and Vera, dooming them all to orphan status, while itself remaining unrealized for the foreseeable future. We'll be left with self-checking HDL benches or C-language hacks for the next two years. Gack!"

John Cooley runs the E-mail Synopsys Users Group (ESNUG), is a contract ASIC designer, and loves hearing from engineers at (jcooley@world.std.com)or (508) 429-4357.