When I first thought about what's new for built-in self-test (BIST) at the recent Design Automation Conference, I thought, as usual, of LogicVision. They're the ones with the big name in BIST. "Fujitsu used LogicVision's logic BIST tool very effectively," one engineer wrote me after DAC. "BIST is most commonly used on RAMs because the patterns are very repetitive and have high fault coverage. The typical knock against using BIST for logic is that you quickly get up to maybe 70 or 80 percent coverage and then it takes gobs of vectors to eke out each additional percent. For example, if there is a zero detect on a 32-bit adder output, random patterns would result in this signal being active only once every 2**32 clocks. In the past, some people have advocated starting the test with BIST, then doing extra vectors for the tough faults. LogicVision has software that identifies where to add extra test points (like a zero flag) so as to get high coverage with fewer clocks. Fujitsu got 99 percent fault coverage with this tool."
"We're using LogicVision memBIST and Formality. So far memBIST looks OK and Formality has been a winner," wrote a second engineer.
"LogicVision has sold tools to insert BIST for RAMs and logic for a few years," wrote a third engineer. "They now have a tool for adding BIST to phase-locked loops (PLLs)."
No big news here. LogicVision has incrementally improved its BIST. Yawn.
Bored, I looked at GeneSys. At first glance, GeneSys was no big shakes either. They had all sorts of basic cores for BIST. Memory BistCore, Logic BistCore, Boundary ScanCore. Yeah, so what? LogicVision's been doing this way before anyone ever heard of cheesy little GeneSys. Yawn.
Then I accidentally found the GeneSys BISTDR. That caught my eye! First, think in terms of their GeneSys Memory BistCore. It's synthesizable and goes right into your chip to do the right thing on power-up (and other times that you trigger it) to automatically test your chip's memories. OK, so it's standard BIST so far. Then, in walks their BISTDR. On power-up, BISTDR tests all your memory and when it finds a problem-it remaps that bad address to a working spare address space.
Clever. When I think of the portions of million-gate-plus chips that are memory, suddenly BISTDR becomes the golden-haired boy everyone loves. Of course, you'll need larger memories in your designs for the spare space to remap to and it's (right now) only a power-up type of mem BIST. (That is, it doesn't fix run-time alpha particle issues.) I'm told it's most effective with 256-kbit memories or larger-but it's parameterized so there's no upper limit if you have the cycles. Neat: http://www.GeneSysTest.com.
John Cooley runs the e-mail Synopsys Users Group (esnug), is a contract asic designer and loves hearing from engineers at "jcooley@world.std.com" or (508) 429-4357.
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