The neat thing about e-mail and having a column in EE Times is that it gives 165,000 readers a chance to add their two cents. The first to write was Cliff Whitmore of 3D Labs. "I'm trying to figure out the actual mechanics of how they make remapping work. Do they rely on a specific memory technology (from a particular vendor), or do they insert logic between my address generation logic and the RAM for the remapping, or do they blow a fuse map at wafer test, or what???"

The second to write was Hank Walker of Texas A&M, who sometimes tersely cuts to the technical chase. He sent me a one-sentence letter. "IBM has done this in their memory BIST engines for many years."

Someone named "YJS" in Taiwan, wrote: "You forgot SynTest for BIST solution. You may like to check their products for different DFT [design-for-test] tools."

And Roderick McConnell of Infineon half-humorously warned me, "Beware: many cells fail only after a while. If you are trying to repair these at power-on, you may end up doing a lot of rebooting. Perhaps you're happy that a 'bad bit' in an SRAM causes the connection to be lost when you are using a mobile phone with a long-winded salesperson who just doesn't stop talking-but that's tough to predict."

But the oddest and most interesting reply came from Jeff Ebert of Sonics. "Have you looked at Virage's Star (self-test and repair) capability yet? We are beginning to use their SRAMs, and this capability looks very interesting," Jeff wrote. "Basically, you get a scan interface to disable addresses and remap them. It's very fine-grained. The overhead is very low, because it is built into the hard macros."

(That was odd because Virage isn't really known in the test world. See for yourself at www.VirageLogic.com. Virage makes COT embedded memory compilers for fabs like TSMC, UMC and Chartered. But it's not all that surprising for them to be testing memories, since they make them.)

I phoned Virage to see what was up. It turns out that Virage's Star generates memories sized from 64k to 4 megs. "We have added redundancy with spare rows and columns in our embedded Star memories," said Alex Shubat, the CTO at Virage. "It can do off-chip test with laser fuse-box repair at manufacture. It lets you skip using a memory tester in fab. Star can also do built-in self-repair on power-up."

And one of my Wall Street buddies later phoned to say that there's a rumor LogicVision was trying to set itself up for an IPO soon. Hmmmm. . . .

John Cooley runs the E-mail Synopsys Users Group (ESNUG), is a contract Asic Designer and loves hearing from engineers at jcooley@world.std.com or (508) 429-4357.