I remember at DAC two years ago when Gary Smith of Dataquest first mentioned the "importance" of virtual silicon prototyping. It was in Gary's annual pre-DAC briefing to the press and EDA CEOs. And nobody there had any idea what this virtual silicon prototyping beastie was that Gary was barking about. (We just figured he was having one of those senior moments that old folks are known to have occasionally. Gary went to high school with Edison, ya know.)
That was two years ago. Now jump to the SNUG gathering from two months ago. During the Aart de Geus CEO Q&A session, Neel Das of Corrent mentioned how he wished PhysOpt (physical compiler) had automatic floorplanning built into it. "I hate that you have to go to a layout tool to make a PDEF to get PhysOpt started," said Neel. "I'd like this to be automatic for blocks."
That's why it was interesting that Synopsys, at the same SNUG, let customers see its experimental PhysOpt-MPC (minimum physical constraints) tool. Basically, MPC is a prototyper for RTL jocks stumbling around in PhysOpt. MPC simply assumes a default floorplan for your block. Your aspect ratio is 0.8, cell utilization is 65 percent, origin is at 0,0, corner keepouts are 100 micrometers, I/O margins are 20 micrometers and the easiest pin placement is assumed.
Using PhysOpt-MPC this way, an RTL jock responsible for a 300,000-gate block in a 5 million-gate design doesn't have to muck around with DEF or PDEF 3.0 floorplans just to get a feel for how his block's timing roughly works. The quick and dirty PhysOpt-MPC runs lets you know if you have a few critical paths and what they are. Or it says that 75 percent of your paths are critical and you have a serious architectural problem with that block.
And by tweaking the MPC defaults, an RTL designer can also find the rough trade-offs in metrics like timing vs. utilization vs. aspect ratios. He can see how a 2:1 aspect ratio with 50 percent utilization may be his fastest design-while at 1:1 and 60 percent, the block has the least congestion. In a nutshell, MPC gives you early physical feedback on your RTL blocks.
Whether this way of prototyping catches on with PhysOpt users is anyone's guess. But one thing is for sure: This pretty much proves to me that Gary wasn't having a "senior moment" when he was discussing silicon virtual prototyping two years ago. What Gary says at this year's DAC is another thing altogether (grin).
John Cooley runs the E-mail Synopsys Users Group (ESNUG), is a Contract ASIC Designer, and loves hearing from engineers at "jcooley@theworld.com" or (508) 429-4357.
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