The old Summit used to pitch"electronic system design automation," its term for graphical design entry EDA tools. The idea behind ESDA was that if engineers think in terms of data paths and bubble diagrams, then the GUI in EDA tools should let engineers enter designs in terms of data paths and bubble diagrams. Summit took the concept further by enabling the design to simulate graphically, too. But the idea failed to catch on.

"Graphical tools help newbies become productive faster, but once the newbie is on the road, the tools are too restrictive-sort of like training wheels," wrote John Weiland of Intrinsix. Having failed to recognize that chip designers feel naked without their Verilog, Summit quietly disappeared.

Fast-forward to DAC 2002. "In addition to their VHDL and Verilog tools, the new Summit has a lot of C-related tools," Weiland wrote. "They have a SystemC graphical environment that allows architectural-level modeling. . . . Summit allows you to hierarchically decompose your C down to [the register transfer level] and then can translate that to RTL VHDL or Verilog. They say RTL level C is 100x faster to simulate than RTL VHDL or Verilog."

Michael Lee of Lucent cited "the Summit FastC approach, which is to write your RTL as C, VHDL or Verilog and use Visual HDL to push it all out together." He lauded "Summit's approach of using a mix of graphical and textual design entry and allowing you to mix up styles. The demo looked nice. . . . The proof, of course, comes when you actually try it out."

Another DAC visitor wrote that "as for Summit's Visual Elite, I was not looking for C-based hardware design at DAC so I didn't spend much time looking at it. I have yet to buy into any C-based system modeling or C-based HW design flow. Too much expertise resides in Verilog."

Stephan van Beek of Oce Technologies hailed Summit's "FastC, which allows you to speed up run-times very dramatically. This may be one of the reasons for us to move toward C."

"I was not particularly turned on by what Summit had to say at DAC," said Darko Gojanovic of Intel. "Still, it warrants a deeper look."

John Cooley runs the E-mail Synopsys Users Group (ESNUG), is a Contract Asic Designer and loves hearing from engineers at jcooley@theworld.com or (508) 429-4357.