Fixing the hold times on scan chains is like working on the septic system of a country house. Nobody praises you for doing it well, but people notice when it's not working right. And I don't want to be worrying about circuits there just to test my design anyway. Like most people, I just like to flush the toilet and forget about it, thank you.

With this in mind, I was happy to publish in ESNUG 404 (http://www.DeepChip.com/posts/0404.html) a letter and some Design Compiler scripts from David Simmons of Toshiba that automatically cleaned up hold time problems on scan chains. "Hold time problems in scan chain shift timing can be fixed by a recompile, of course, but care must be taken to keep Design Compiler from doing anything to create problems with functional logic. This usually requires multiple compile scripts with 'case' statements and repeated timing runs to monitor dc's effect on the netlist," David writes. "Reordering the scan chain in order of clock delays is another solution to fixing scan shift hold time problems, but it's somewhat more complicated to automate."

Although I haven't had a chance to try David's scripts on a customer's chip yet, I did take a quick look to see how they worked. Basically he searches for hold violators on the TI pins in all flip-flops in your design and then he repeatedly buffers up their inputs (as a post-layout ECO) until the hold times are met.

I liked his clever use of date codes in the buffering iteration process. "The date code prevents identical-instance names from being generated in the unlikely event that the script finds the same error twice on the same design, in successive ECO cycles," reports David.

And in all modesty, David doesn't claim his scripts are perfect. "One thing to keep in mind is that when inserting cells in a post-layout, SDF-annotated netlist, new nodes are created for which SDF annotation will not exist and which will be timed using whatever other timing parameters Design Time can find (typically wire loads)," he warns. "So as the script repeatedly runs looking for hold violations, it may inaccurately assess the remaining violations from inaccurate timing due to missing SDF annotation. Worst case, this results in another ECO cycle. I will fix this problem some time in the year 2073, when the EDA industry has finally succeeded in interactively coupling layout with synthesis."

David's perfectionism aside, I'll be using his scripts in my next chip.

John Cooley runs the e-mail synopsys users group (esnug), is a contract asic designer and loves hearing from engineers at jcooley@theworld.com or (508) 429-4357.