When Synopsys CEO Aart De Geus stood up to give his key-note address at DVcon'03, nobody expected him to say anything controversial. It's not Aart's style. So when he gave a talk on the history of the productivity gap in EDA for the past 20 years, we all thought that everything was normal.

But subtly, during that talk, Aart put up three slides that showed Verilog and VHDL as being what's here now, with only System Verilog being in the future. His final slide had an overlay stating that System Verilog is 100 percent backward-compatible with Verilog and that it thus will succeed because it will let you keep all your old Verilog legacy code. Aart closed his speech by stating that Synopsys is committed to developing System Verilog synthesis, simulation and analysis tools.

It was as if a smart bomb had hit the room. The trade press and Wall Street considered the comments no more than a pitch for System Verilog. But my fellow chip designers clearly saw the writing that Aart had put up on the wall. Verilog and VHDL may be here now, but in the future only a flavor of Verilog will be left.

"I think Aart just said that VHDL is dead," Cliff Cummings, president of Sunburst Designs, said to me in the awkward 30 seconds that followed Aart's speech. "At least, that's what I think he said."

Consultant Stu Sutherland agreed with Cliff. "He said VHDL has no future. That sounds pretty dead to me."

In the confusion, I got picked to approach Aart and ask him what he had meant in his comments about VHDL.

Aart replied that his R&D group isn't developing any new VHDL-based products, but he also said it will take years to phase out VHDL because leaving customers in the lurch would be bad form. In short, he wasn't abandoning VHDL as much as promoting System Verilog.

"This is a big statement. We are putting the Synopsys weight behind this language for RTL plus design," Aart said. "I do believe in the long term, though, that System Verilog will be the dominant language."

So after years of the Verilog vs. VHDL wars, in one speech, Aart had kicked VHDL out of the big-money ASIC flows. And VHDL became the new Latin; a dead language supported only by a few obscure, devout holdouts in the small-money FPGA world. Verilog (make that a beefed-up Verilog) had won.

John Cooley runs the e-mail synopsys users group (ESNUG), is a contract asic designer and loves hearing from engineers at jcooley@theworld.com
or (508) 429-4357.

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