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Max Bytes
Noted author and commentator Clive "Max" Maxfield presents an entertaining view of the cutting edge of IC, PCB and system-level EDA tools and methodologies.
Cool EDA products light up 2005 (08:10 PM EST, 03/14/05)
Turning software into hardware (01:42 PM EST, 03/02/05)
Got system-level synthesis? (02:12 PM EST, 02/18/05)
True DSP synthesis at last? (08:54 PM EST, 02/03/05)
Cool EDA offerings for the new year (06:54 PM EST, 12/30/04)
Altium add-ons boost FPGA support (12:56 PM EST, 11/10/04)
Catalytic adds key piece to ESL puzzle (01:03 AM EDT, 10/20/04)
Verification IP complexity approaches design IP (07:55 PM EDT, 09/16/04)
Simulator boggles the mind (02:00 PM EDT, 08/26/04)
PCI Express made easy (06:00 PM EDT, 07/30/04)
Going virtual speeds SoCs (10:00 PM EDT, 07/18/04)
Celoxica adds new C tools (07:00 PM EDT, 07/01/04)
'Vast' speedup in simulation (02:00 PM EDT, 06/15/04)
Catapulting C to success (01:00 PM EDT, 06/03/04)
Making PCB design easier (01:00 PM EDT, 05/20/04)
FPGA book tells all (12:00 PM EDT, 05/04/04)
VIP verifies PCI Express (01:00 AM EDT, 04/20/04)
Synopsys 'ARMs' SystemVerilog (08:00 PM EDT, 04/05/04)
'Live' toolkit does it all (01:00 PM EST, 03/17/04)
QuickSilver's silicon-to-go (02:00 PM EST, 02/24/04)
New approach to assertions (01:00 PM EST, 02/06/04)
Moving to RTL floorplanning (06:43 PM EST, 01/16/04)
RTL models fly at KHz speeds (08:56 PM EST, 01/05/04)
Digital test in a 'pod' (05:33 PM EST, 12/18/03)
Do-it-all FPGA design toolkit (07:48 PM EST, 12/01/03)
RTL analysis saves time (06:34 PM EST, 11/18/03)
Fast ASICs with structure (01:00 PM EST, 10/31/03)
Planning ahead for FPGAs (08:57 PM EDT, 10/15/03)
Do-it-yourself science CDs (07:37 PM EDT, 09/24/03)
ASICs find new 'structure' (12:54 PM EDT, 09/03/03)
A cool way to save power (01:07 PM EDT, 08/19/03)
Help me write my FPGA book (01:57 PM EDT, 08/04/03)
Workstation in a briefcase (07:33 PM EDT, 07/14/03)
Power analysis on steroids (02:13 PM EDT, 06/30/03)
Emulation with a difference (08:24 PM EDT, 06/17/03)
New language makes waves (09:43 PM EDT, 05/29/03)
A 'Vast' move in codesign (05:53 PM EDT, 05/15/03)
Free software aids disabled (02:20 PM EDT, 05/01/03)
New look for HW/SW debug (02:14 PM EDT, 04/17/03)
GDS Builder 'ReShapes' ICs (11:05 AM EST, 03/24/03)
Taming the analog 'dragons' (06:53 PM EST, 03/07/03)
0-In eases verification tasks (01:34 PM EST, 02/17/03)
Useful tidbits for designers (09:36 PM EST, 02/03/03)
Logic analyzer gets personal (07:02 PM EST, 01/16/03)
Perforce Manages H/W and S/W (07:39 PM EST, 01/02/03)
Dancing the 'Boolean Boogie' (02:09 PM EST, 12/17/02)
PicoChip offers parallel idea (05:13 PM EST, 12/03/02)
Adaptive silicon comes to RF (06:28 PM EST, 11/01/02)
Silver bullet for ACMs (07:10 PM EDT, 10/14/02)
Reconfiguring chip design (07:37 PM EDT, 09/27/02)
IC prototyping done right (02:57 PM EDT, 09/13/02)
News nuggets from Xilinx, Axis and Mentor (02:05 PM EDT, 08/30/02)
Walking the assertion maze (01:29 PM EDT, 08/15/02)
A plethora of languages (01:41 PM EDT, 08/01/02)
New approach to translation (08:24 PM EDT, 07/12/02)
Accelerating confusion (06:37 PM EDT, 07/01/02)
Small companies, big breakthroughs (04:57 PM EDT, 06/19/02)
Good behavior for debugging (02:20 PM EDT, 05/31/02)
Why properties are important (01:20 PM EDT, 05/15/02)
ACM chip beats ASICs (12:00 PM EDT, 04/29/02)
How Monterey designs chips (02:08 PM EDT, 04/16/02)
Reader doubts Magma claims (06:16 PM EST, 03/29/02)
How Magma makes timing (06:45 PM EST, 03/15/02)
Adaptive ICs up-end EDA (07:31 PM EST, 02/28/02)
Homegrown tools rock (07:37 PM EST, 02/12/02)
Who is that masked man? (01:55 PM EST, 01/11/02)
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