These tools, which are created to address a specific need, can be amazingly useful. In the very early 1980s, for example, the small company I was working for decided to design and build a RISC hardware accelerator. The lack of memory and power inherent in computers of that era meant that simulating this beast using a commercial event-driven approach would have taken an unacceptable amount of time. It would probably still be running today, now that I come to think about it!

To solve this problem, our programmers whipped up a simple cycle-based simulator. Although not tremendously sophisticated, this little rascal allowed us to perform hardware/software co-verification by running the full operating system (OS) on a model of the entire hardware accelerator. I remember seeing a simulation run go all the way through the power-up sequence, eventually displaying the OS command-line prompt on the screen. This was amazingly cool for the time.

ParaCore Architect

All of this was brought back to me recently when I was working on a project with Tom Dillon of Dillon Engineering. Tom's company offers a variety of custom design services, with particular emphasis on FPGA-based DSP algorithms and high-bandwidth, real-time digital signal and image processing applications.

A few years ago Tom's engineers realized that they were constantly reinventing things like floating-point libraries, convolution kernels, and Fast Fourier Transform (FFT) processors. To make their lives easier, they developed a tool called ParaCore Architect. This application accepts a source file containing a highly parameterized description of the design at an extremely high level of abstraction. It combines this description with parameter values specified by the user, and generates an equivalent HDL representation along with an associated testbench.

For example, several FPGAs now come equipped with a microprocessor core, but without a floating-point unit. So ParaCore Architect can be used to generate a corresponding floating-point core. Different parameters can be used to set whatever exponent and mantissa precisions are required, how many pipeline stages to use, whether or not to handle IEEE floating-point special cases like infinity, the type of microprocessor core, and so on.

Similarly, in the case of an FFT, different parameters can be used to select the number of points to be processed, choose integer versus floating-point math, decide whether to use internal memory structures or force the use of external memory, determine the number of butterfly structures to be implemented in hardware, and so forth. In fact, ParaCore Architect recently helped create what is possibly the fastest FFT processor in the world. (This is now being used by the SETI project to process huge amounts of data from radio telescopes in the search for extraterrestrial intelligence).

What is really cool is that Tom is planning on making this tool available for use over the web. When you're creating something like an FFT, you often want to experiment with different trade-offs, such as how many bits to store for each point. Tom's idea is that you could visit their web site, select the type of core you're interested in, specify a set of parameters, and press the "Go" button to generate the equivalent HDL and testbench.

More Free Stuff

For anyone who is interested, a homegrown logic synthesizer and do-it-yourself logic simulator are available at the Techbites web site for you to download and play with. And if you have any homegrown tools of your own, please don't hesitate to email me and tell me about them.

Until next time, have a good one!

Clive (Max) Maxfield is president of Techbites Interactive, a marketing consultancy firm specializing in high-tech. Co-author of the book "EDA: Where Electronics Begins," Max was once referred to as a "semiconductor design expert" by someone famous who wasn't prompted, coerced, or remunerated in any way.