One of the things that had my head spinning was the morass of design languages, and how folks think they are all going to play together. These include SystemC, Verilog 2001, System Verilog, and Superlog, and don't get me started on the plethora of property/assertion languages that are now roaming wild and free. I'm still mulling all of this over in what used to pass for my mind, and am planning on making it the topic of a future column. In the meantime, I'd like to introduce just a few of the companies and products that caught my eye.

Summit is back
Way back in the mists of time when I was still a young man, I was working for Intergraph Electronics (which eventually became VeriBest before being acquired by Mentor a couple of years ago). Anyway, in 1990 Intergraph Electronics acquired Dazix (itself the result of the merger between Daisy and Cadnetix), which included a cutting-edge development team in Israel.

That team eventually went on to form a company called Summit Design. Some time later Summit merged with Viewlogic to become Innoveda. In April 2002, Summit emerged from Innoveda as an independent company once more, while the rest of Innoveda was acquired by Mentor.

Of course, I bounced over to the Summit booth to see a few old friends, and stayed for a demo of their latest system simulation offering, which is called Visual Elite. Things have certainly moved on from the old days, when the ability to co-simulate Verilog and VHDL was considered to be pretty exciting. Visual Elite allows you to freely mix System C, C/C++, Verilog, and VHDL, to simulate them all together, and to display the results -- signals and abstract data -- in a common waveform viewer.

You can of course code everything by hand, but you can also save yourself a lot of pain by using their graphical block-level capture system. This allows you to partition the design into blocks and specify the language associated with each block. You can then push into a block to capture its contents using the text editor of your choice. The advantage of using this graphical approach at the highest level is that all of the inter-block communication and simulation tasks are handled behind the scenes, transparent to the user.

Simucad and Silos-64
Of course the "big boys" of EDA always attract a lot of attention, but personally I have a soft spot for the smaller companies who keep on honing their tools and, in many cases, offering excellent value for money. One such company is Simucad with their Silos-64 Verilog logic simulator.

Silos-64 comes equipped with powerful, intuitive graphical user interface, featuring a combined hierarchy browser and source code viewer/editor, a finite state machine editor, and a waveform viewer. This interface also sports some very nice features like a code coverage display (the code coverage analyzer itself is fully integrated with the simulator).

Silos-64 is a full-blown extremely powerful Verilog simulation engine with all of the bells and whistles we've come to expect. What is unusual is its price tag, which is extremely reasonable at only $4,000 per seat. The price is the same irrespective of the target platform: Linux, Sun, or PC. This makes Silos-64 very interesting to smaller ASIC and FPGA design houses and design consultants.

LogicVision and their Validator
On the hardware side of things, I was really interested in LogicVision and their new Validator box. As we all know, an IC design isn't really finished until you get your first silicon back from the foundry --and it works. Unfortunately, there really isn't an integrated tool flow that takes you all of the way through design to silicon debug, so if your first batch of silicon chips doesn't work, you have something of a problem.

The three classic ways of testing a new device are (a) the brute force approach of putting it into the real system; (b) creating a special-purpose performance board whose sole job is to test the device at speed; or (c) using a chip tester from someone like Teradyne (in which case you need to plan on shelling out $3 million or more). The fundamental problem with all of these techniques is that they typically provide you with Pass/Fail type information. In the case of a Fail, you are presented with the failure data, but this doesn't really help you to determine the cause of the fail. The end result is that it can take a huge amount of time to debug the silicon.

LogicVision's answer is to take a design and embed a number of built-in self-test (BIST) modules associated with the logic, memory blocks, processor cores, PLLs, and so forth. Remembering that most devices these days are pad limited rather than silicon limited, the fact that these BIST modules increase the transistor count by 1% to 3% isn't terribly significant (and the larger the device, the smaller the relative overhead).

Once you get your first silicon back, you just connect it up to the Validator box. You don't have to create any programs or test vectors - you just make the embedded test database associated with your design available to the Validator. What's really cool is that if the chip fails in any way, you aren't simply presented with the I/O data. Instead, the Validator employs advanced conic statistical analysis techniques to resolve the error down to a particular net or gate. And LogicVision told me that they have new analysis tools in development that will resolve errors down to individual transistors.

Of course one always hopes for first time silicon success, but if the fates are against us, then having something like the Validator that can detect, locate, and identify a failure mechanism in hours (rather than days, weeks, or months using traditional techniques) has got to be a good deal.

And the cost? The big cheese in LogicVision's booth - Mukesh Mowji - vice president of marketing (who I would like to note was a real nice guy who took a lot of time to explain things in words even I could understand) told me that the box is only $150,000 including software, and it's available for immediate delivery. If the Validator (plus associated software) can do everything LogicVision claims, then it could pay for itself on its first day in action, which has got to be a good deal whichever way you look at it.

You've been tagged!
This DAC was a lot of fun for me in many ways, not the least that my daughter Abby came down with me. In addition to making sure my shoes were tied and that I ended up in the right place at the right time, Abby's task was to support the EDA Consortium by handing out their new DVD entitled "EDA: Where Electronics Begins." (As an aside, this 15-minute presentation - which is available in English, French, German, and Japanese on the same disk - provides a really great introduction to what EDA is for a non-technical audience.)

As her real job, Abby runs our GottaGlow glow-in-the-dark novelty company, so we couldn't resist taking a load of chemical glow bracelets with us. Our original intention was just to hand them out at the evening parties, but Abby pointed out that we were actually "tagging" the people we'd talked to. (I said "Have I talked to that guy yet," and Abby replied "You can't have, he's not been tagged!") As you can imagine, this made it really easy to spot any un-tagged folks we still wanted to meet.

New Orleans was a blast -- the parties were great - and DAC had plenty of new and improved hardware and software tools for me to play with, all of which has to be worth an official "Cool Beans!" Of course I've only touched on a few of the companies and products here, and I'll be regaling you with more nuggets of information on different people and tools over my next few columns. Until next time, have a good one!

Clive (Max) Maxfield is president of Techbites Interactive, a marketing consultancy firm specializing in high-tech. Author of Bebop to the Boolean Boogie (An Unconventional Guide to Electronics) and co-author of EDA: Where Electronics Begins, Max was once referred to as a "semiconductor design expert" by someone famous who wasn't prompted, coerced, or remunerated in any way.