However, I was somewhat puzzled when the PR guru from Tharas sent me an email asking if I'd care to drop by their booth to see their new hardware simulation accelerator called Hammer that can handle "an amazing 32 gates." I responded that I could probably build a 32-gate accelerator out of the components lying around on the floor of my office, and she immediately replied along the lines of "Eeeeekkk, I meant to say 32 million gates," which is obviously a duck of a different feather.

"When your only tool is a hammer ....
... everything looks like a nail," as the old saying goes (sorry, I couldn't resist). Actually, the Hammer is a pretty cool box. Remarkably small at only 20 inches tall by 10 inches wide by 20 inches deep, a low-end box that can handle 2 million equivalent (2-input NAND) gates costs only $115K, while the full-up version that can simulate 32 million gates (and also has 4 GBytes of spare memory to handle such things as memory blocks) costs only $780K.

Obviously these amounts of money aren't chickenfeed, but they compare very favourably to similar boxes from the "big boys" that can be in the order of $1.5M for 16 million gates. Of course, the purveyors of those boxes would say "But we can do this, and this, and ..." at which part your head quickly starts to spin, because the amount of confusing and contradictory information that everyone threw my way made what little hair I have left stand on end.

So let me tell you a little bit more about the Hammer, and then we'll discuss the other offerings. First of all it's important to note that the Hammer is great for hardware simulation acceleration. Its compile times are said to be as fast as those of a software simulator (approximately 1 million gates take around six minutes), and it speeds RTL-level simulations by 10 to 50 times depending on the circuit, while gate-level simulations typically run in excess of 1,000 times faster.

Unusually, the Hammer can be used to accelerate behavioral constructs in addition to RTL and gate-level descriptions. On the downside, it works with Verilog design representations only. Furthermore, the Hammer is intended for use only as a simulation accelerator, which means that the design under test (DUT) is loaded into the box, and the stimulus and response checking is provided in the form of a testbench in C or Verilog. At this time, the Hammer cannot be used in an emulation mode, in which the stimulus fed to the DUT comes from a real system and the responses from the DUT are fed back into the real system. This is obviously a bit of a showstopper if you need emulation capability, but not everyone does, and if simulation acceleration is all you require then the Hammer looks pretty tasty.

There are two main forms of hardware simulation accelerators/emulators. The first is based on using circuit boards populated with lots of special ASICs, each of which contain a number of specialized processors and lots of local memory (typically 80% to 90% of these devices are memory). In this case, the HDL representation of the design is compiled into machine code, which is subsequently distributed amongst the various processors. The alternative is to use circuit boards populated with FPGAs, in which case the HDL design is typically synthesized down into a gate-level equivalent, which is partitioned across, and loaded into, the various FPGAs.

The Hammer is of the processor-based variety. Other points worth noting are that every signal in the design is available for debugging (you have 100% signal visibility and 100% memory visibility), and that simulation results are dumped to the host processor via a 2 GByte/sec fiber optic cable. (The simulation results are double-buffered, so while one buffer is being filled the other can be downloading to the host processor without affecting the simulation speed.) Simulation results can be dumped in standard VCD format or in the Novas fast signal database (FSDB) format. Last, but certainly not least, four Hammers can be connected together to provide the capability of simulating 128 million gate designs (wow!).

The quickness of the hand deceives the eye ...
After being regaled by the wonders of the Hammer by the folks at Tharas (who were all jolly nice quys and gals let me say), I meandered off to investigate the alternatives, and quickly found myself neck deep in a quagmire of confusion and - dare one say - in some cases misdirection.

First I ambled over to the Cadence booth to look at a Quickturn Palladium. Quickturn was of course acquired by Cadence some time back. Having not seen one in the flesh before, I was somewhat taken aback by the Palladium's size, which is approximately that of a typical English fridge. However, I was very impressed when I heard that this little rascal was scalable from 2 million gates (and 1 GB of spare memory) to 128 million gates (and 64 GB of spare memory). Having said this, I was somewhat less impressed a little later on when I trundled over to the Mentor booth to see the latest Ikos box (Ikos was of course recently gobbled up by Mentor). When I mentioned the Palladium's 128 million-gate capability, they sniggered at me and pointed out that his was only true if one connected eight of these fridge-sized units together.

It turns out that each Palladium can handle a maximum of 16 million gates - a little fact that the guys I was talking to on the Cadence booth may have felt was a little too technical for me to understand, so they attempted to save me from any confusion by neglecting to pass on this gem of information (thanks lads, I appreciate your concern [grin]).

One thing I did think was rather interesting and useful is that the Palladium, which is also processor based, can support up to sixteen simultaneous users. This means that you can apply different portions of the available capacity to different projects, or to multiple instantiations of the same project. It may be that one or more of the others do this also, but I forgot to ask.

With regard to the Mentor/Ikos box, which is about the same size as a Palladium, this FPGA-based unit is called the VStation-30M because it can handle up to 30 million equivalent gates. This little rapscallion also looks rather cool, which is of course an important consideration for today's young engineers about town.

I also ran across the Xtreme-II from Axis Systems. About the same small size as the Hammer, this FPGA-based unit is said to be capable of simulating 50 million equivalent gates (or 100 million gates if you strap two Xtreme-IIs together). Truth to tell, the Axis folks started to look a little furtive when I asked, "Are these 50 million real gates?" (By this time I was learning which questions made people wince). However, it turns out that unlike other FPGA-based boxes where the route is RTL to synthesis to gates, Axis claims to somehow map portions of the RTL directly into the FPGAs, which makes equivalent gates a bit harder to tie down.

And then things started to get confusing...
The problem I quickly ran into on my seemingly endless quest for the truth is that every time I talked to anyone they presented me with a new nugget of information that I hadn't thought to ask anyone else. For example, Axis pointed out that they used an event-based simulation algorithm as opposed to a cycle-based approach such as that used by the Palladium. Is this important in hardware acceleration/emulation? To be honest I don't have a clue, and after crawling around the Tharas/Quickturn/Ikos/Axis trail for the "nth" time I could care less, because my head was full and it felt like my brains were starting to leak out of my ears.

Ultimately, it all depends on what you need and how much money you have to throw at the problem. Quickturn and Ikos have been playing this game for a long time, and I'm perfectly happy to accept their claims to have incredibly cunning and powerful technology. Unlike the Hammer, the Palladium, VStation-30M, and Xtreme-II can all be used for both simulation acceleration and emulation. However, these boxes can also be rather expensive.

Convincing anyone from Quickturn, Ikos, or Axis to give me an actual price for anything proved to be beyond my powers of persuasion. This is fair enough, I suppose, because everything is subject to negotiation and what you end up paying is rarely the same as the initial asking price (in my case I usually end up paying more). But it does make comparisons difficult. Suffice it to say that I was told the VStation family ranges from around $500K to around $6M (and I was coyly informed that that 30 million-gate version tended to the upper end of this spectrum).

I didn't get any reliable data on the Palladium pricing (although I wouldn't be surprised if it was on a par with the VStation family), and the Axis folks told me that I could walk away with a fully loaded box for "less than $5M." They so obviously considered this to be a real bargain that I almost bought one for my mother for her birthday!

So where do we go from here?
I'd really like to sit down with someone who has had "hands-on" experience with all of these boxes and who is in a position to clearly articulate the advantages and disadvantages of each. In the real world this isn't going to happen of course, so if you are looking to purchase something of this ilk, be prepared to ask lots of questions.

Personally, I thought that the Hammer could be very interesting for design teams on a limited budget, and who were happy with simulation acceleration without emulation capability. But there are so many factors to juggle that it's difficult to know which way to jump. As the "Prize" said in "Where is Earth?" by Robert Sheckley: "Be admiring but avoid the fulsome, take exception to what you don't like, but don't be stubbornly critical; in short, exercise moderation except where a more extreme attitude is clearly called for." I couldn't have said it any better myself! Until next time, I remain ... fond of ice cream!

Clive (Max) Maxfield is president of Techbites Interactive, a marketing consultancy firm specializing in high-tech. Author of Bebop to the Boolean Boogie (An Unconventional Guide to Electronics) and co-author of EDA: Where Electronics Begins, Max was once referred to as a "semiconductor design expert" by someone famous who wasn't prompted, coerced, or remunerated in any way.