Now, my core expertise is in digital logic design, even though I was designated as the analog product marketing manager in one of my past lives. This means that I've typically tended to avoid the physical design (place-and-route) portion of the design flow, for which I'm truly thankful. All I really know is that physical design is painful and extremely time-consuming, so I was amazed to hear ReShape's claims to be able to take multi-million gate designs from netlist to GDSII in less than 24 hours. "Pull the other one, it's got bells on it," I thought, but having chatted to the folks at ReShape I really think they have some interesting technology.

Let's set the scene
Before we plunge into ReShape's offering, we first need to set the scene. Today's typical physical design goes something like this. The design is split into blocks, each of which is placed and routed individually. Eventually these blocks are integrated (connected) together at the chip level, which is where your problems really start.

This is a labor-intensive process that generally requires an engineer working on every one or two blocks. The integration is difficult and often slips, and even best-in-class solutions may take up to three weeks to complete each full-chip build. Also, another consideration is that it is typically not possible to reuse a "chip build recipe" for any derivative designs in the future (this is becoming increasingly important, because the use of derivative designs is on the upswing).

Apart from anything else, the majority of today's designs feature channels between blocks, where these channels are used for the global (block-to-block) interconnect. To illustrate the problems with this approach, let's assume that we have three blocks called A, B, and C placed side by side. Connections from A to B and B to C will be relatively efficient, but connections from A to C will have to be routed around B. In addition to increasing the latency of the global signals, this approach often ends up with tracks running in parallel for long distances. This results in coupling problems, which requires you to increase the spacing between the tracks, which increases the size of the channels, which pushes the blocks further apart, which increases the latency of the global signals, which ....phew!

The answer is to use abutted floorplans, in which the block boundaries are adjacent to each other. In this case, each block's routing resources are used to realize both local and global routing (in the above example, a track from blocks A to C would pass directly through block B). If B is large enough the signal may need one or more repeaters (buffers), but it will require less of these than going round block B, and the signal's latency will be significantly smaller.

Now many of the big EDA vendors boast that their tools allow you to work with abutted floorplans -- and who am I to cast aspersions? When I come to think about it, however, one rarely sees any pictures of die that were created using this technique. Hmmm, could it be harder than we are lead to believe?

Explaining GDS Builder
First of all we need to be clear as to exactly what we are talking about. My first impression was that ReShape had invented yet another place-and-route-and-stuff tool. "Good grief, here we go again," I muttered to myself." But no, it's not like that at all, because ReShape's GDS Builder complements (and preserves your investment in) existing physical design tools from vendors like Cadence, Synopsys, and Mentor.

GDS Builder actually comprises a number of expert knowledge bases that make your existing tools work like they are on steroids. These include:

• The Flow knowledge base
• The Tool knowledge base
• The Design-specific knowledge base
• The Physical knowledge base

Each tool is regarded as a "Stage Element." GDS Builder provides the "secret squirrel sauce" that allows you to specify how the various stage elements are to be used in the flow without having to worry about scripts, file formats, where data is stored, and so forth. What this means is that you can quickly and easily customize an existing flow (for example, adding a new tool into the flow) or create a completely new flow.

When you actually use GDS Builder to execute a flow, it invokes and controls the various tools. GDS builder kicks off (and manages) hundreds or thousands of independent tasks and acts like the conductor of an orchestra making sure that everything happens at the right time.

Another key element of GDS Builder is the Design Knowledge database and the concept of Design Aware Optimizations. Every time the chip passes through GDS Builder it remembers how the device was built "last time" and re-uses this knowledge as part of the new run (the same way a real live engineer would do things). This "construction by correction" is the way things typically end up being done (as opposed to the "correct by construction" buzz words we hear so often but experience so rarely). This dramatically speeds up iterative runs, and also makes GDS Builder exceptionally useful when in comes to performing derivative designs.

The proof of the pudding
When it comes to benchmarking the physical design portion of a chip, there are two main aspects that need to be considered:

• The time it takes to build the chip for the first time.
• The time it takes to re-build the chip following changes in the netlist and/or floorplan.

What really impressed me is that ReShape actually has real-world devices created using GDS Builder. One example resulted in an area reduction of 35%, which is no small beans, let me tell you (Figure 1).

Figure 1 - Comparison of customer versus GDS Builder implementations

Remember that GDS Builder accepts the same initial design specification as the original flow -- floorplan, netlist, timing, chip I/O map -- it just does things faster and better. Another example features the re-spin of a large-production-run device. The original version of this device reflected a reasonably efficient implementation, but GDS Builder still managed to shave 15% of the area (Figure 2).

Figure 2 - Another comparison of customer vs. GDS Builder implementations

With the best will in the world, after creating a new tool, many EDA vendors effectively end up using their customers to de-bug it (I say this because I've been one of those customers more times than I care to remember). By comparison, ReShape took an alternative approach in the case of GDS Builder, which was to become its own first customer.

They did this by forming a design center to process end-user designs (the first external customer shipment of GDS Builder is planned for Q2 2003). They currently have 7 tapeouts ... 8 tapeouts ... .9 tapeouts ... 'n' tapeouts to their credit (they are furiously working on new designs and the number goes up every time I talk to them).

Of course there's way more to GDS Builder than we can go into here, but from what I've seen this is going to be a "must have" for design teams working on medium to high-end ICs and SoCs, which means that it certainly rates an official "Cool Beans" from me.

Postcript: Interra proliferates Verilog-2001
Another item of note: Interra Systems kindly informed me that they were announcing Verilog-2001 support for their analyzer and test suite. My first thought was "Wow, that's great news." This was closely followed by another musing along the lines of: "Who the heck is Interra Systems, and what analyzer and test suite are we talking about?"

Well, it turns out that most of us have used Interra's products at one time or another, even if we didn't know it. Over the last few years the little rapscallions have devoted themselves to developing a suite of EDA building blocks (like Verilog and VHDL analyzers) that are repackaged and used by most of the major EDA vendors as front-ends to their synthesis and simulation tools.

In fact, Interra has quite a range of memory design and EDA building block tools and test suites available. This means that if you are a small EDA start-up, then rather than "re-inventing the wheel," you can concentrate on your innovative new core product and use Interra's "stuff" as a front-end.

Until next time, have a good one!

Clive (Max) Maxfield is president of Techbites Interactive, a marketing consultancy firm specializing in high-tech. Author of Bebop to the Boolean Boogie (An Unconventional Guide to Electronics) and co-author of EDA: Where Electronics Begins, Max was once referred to as a "semiconductor design expert" by someone famous who wasn't prompted, coerced, or remunerated in any way.