Actually, when I come to think about it, we really didn't have any EDA-type tools at our disposal. In fact, no one of my acquaintance could even afford an electronic calculator. We started off by capturing our ASIC design as hand-drawn schematics. When it came to logic optimization, we had a guy on the team who had a size-16 brain with "go-faster stripes."

This hero would take our circuit diagrams, ponder them for a while, then re-generate them using only a fraction of the original logic (we subsequently spent the rest of the day desperately trying to understand how the new version of our design could continue to perform its magic with so few gates). Sometime later, we performed our equivalent of static timing analysis using the loading tables from the cell library data book, a pencil, and a piece of paper. Ah, the good old days!

But, as usual, we digress. As I was saying, in those days power consumption really wasn't much of a factor. Our circuit boards were mounted in a mainframe computer chassis, while the system's power supply was sufficient to light a small town. There was of course no talk about portable, wireless electronics (barring the latest in transistor radios, which typically used less than ten transistors on a bad day).

By comparison, these days everyone sports a plethora of portable, wireless devices like cell phones with so many features they make your head spin. For example, having dropped my old cell phone in a swimming pool over the weekend (don't ask), I picked up pretty much the cheapest replacement I could. While playing with this little rapscallion, I discovered that — in addition to acting as a calculator, personal organizer, alarm clock, and other functions I don't actually understand yet — it can locate and call numbers using speech recognition (I thought this was amazingly cool and spent the rest of the evening calling people for no reason whatsoever).

But time has moved on, and the power consumption and power grid design of today's digital ICs now forms one of the more significant aspects of the entire design process. That's why the big EDA vendors are spending so much time boasting the advantages of their power analysis tools. The interest in the power problems also provides an opportunity for specialty EDA companies and start-ups to come up with something new and innovative.

Apache's new RedHawk-SDL

Which brings us to Apache Design Solutions and their recently announced RedHawk-SDL (where the "SDL" stands for Static, Dynamic, and Inductance).

From all accounts, RedHawk-SDL is a power analysis tool on steroids. First of all, it analyzes the chip and accounts for all on-chip and off-chip (packaging) inductance and decoupling capacitance effects. In the case of the latter, the guys at Apache brought up an interesting point that I'd not previously considered, which is that there are intrinsic decoupling capacitance effects associated with signal and power grid track segments. RedHawk-SDL takes these into account, and then advises you on any additional decoupling capacitances that you need to add explicitly.

Apache has their own Spice engine called NSpice that you use to accurately characterize the cells forming the cell library. In order to run dynamic analysis, you also need to perform a full-chip static timing analysis (STA) using PrimeTime in order to capture the timing windows of interest. RedHawk-SDA can then perform a vectorless dynamic power analysis that fully accounts for timing windows and cell level power effects (such as leakage and switching power).

The guys and gals at Apache are very bullish about their new technology. They say that they can perform a static analysis in minutes that would take hours using other folks' technologies, and that they can perform a full-chip dynamic analysis in hours that simply wouldn't be possible using other technologies. Of course, doing things fast isn't a lot of good if you sacrifice accuracy, but sample waveforms comparing a SPICE/transistor-level simulation with its RedHawk-SDL cell-level equivalent appear to show an extremely high correlation (Figure 1).

Figure 1 -- Comparison between Spice and RedHawk-SDL

Equally impressive is the capacity of these tools. Apache points to a recent customer who wanted to analyze the effects of full-chip I/O SSO (simultaneously switching outputs). The numbers here are sufficient to make my mind boggle. After I/O and power mesh extraction, the full-chip Spice netlist (including the power-ground network, buffers, and package models) contained 310 I/O buffers, 50,000 MOS devices, and 2.5 million RLC elements.

Using Apache's tools, however, the total runtime for this analysis was under 4 hours on a Linux machine with peak memory consumption running around 1.2 GBytes. (Apache points out that their customer's previous solution using all the Spice licenses they own was restricted to 30 buffers with less accuracy, and the run was at least an overnight job.)

One slight fly in the ointment (to my mind) is that, although RedHawk-SDL can do a fantastic job analyzing voltage drop effects, feeding these results to the STA tool (PrimeTime) to re-calculate the timing windows is an iterative process. It seems to me that there is a real need for these tools to work concurrently, such that the results from the power/voltage drop analysis are immediately and concurrently used to re-calculate the timing windows so as to see if any violations have occurred and to fix them on-the-fly.

Of course, it's always easy to be a critic, and this doesn't take away from the fact that RedHawk-SDL seems to be an incredibly powerful tool that deserves a look at from you and an official "Cool Beans" from me! Until next time, have a good one.

Clive (Max) Maxfield is president of Techbites Interactive, a marketing consultancy firm specializing in high-tech. Author of Bebop to the Boolean Boogie (An Unconventional Guide to Electronics) and co-author of EDA: Where Electronics Begins, Max was once referred to as a "semiconductor design expert" by someone famous who wasn't prompted, coerced, or remunerated in any way.